JPS58144959A - Controller - Google Patents

Abstract

PURPOSE:To perform more controls quickly, by accessing freely a memory, which is connected to a CPU, directly from an external device wihtout setting the CPU to the holding state. CONSTITUTION:A memory map is allocated by an address decoder 8, and an ROM 3 is used as a program area, and an RAM 1 is used as a data area. The data transfer between an input/output port 6 and the RAM 1 is controlled by an I/O data buffer 9. Addressing of the RAM 1 due to an address counter 7 is controlled by an I/O address buffer 10. A bus control circuit 11 is connected to a CPU 2 through a control bus. The bus control circuit 11 controls buffers 4, 5, 9 and 10 to make it possible to access the RAM 1 from the input/output port 6 at the timing of a machine cycle M1 and to access the RAM 1 from the CPU 2 at other timings.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device having a CPU (Central Processing Unit) and a memory. CPU
The memory connected to the computer can be directly accessed by an external device.

Control may be performed using an MPU (micro processor unit). In this case, C.P.
It is necessary to write the status of the control system to the memory that U accesses, and to read commands to the control system from that memory.

It is conceivable that k, which transfers data between the memory accessed by the CPU and an external device, executes a predetermined instruction in the III K CPU. In this case, the data (status) of the external device must be
To transfer the data (commands) from the memory to the accumulator, etc., and then write the contents of this accumulator, etc. to the memory, or vice versa, read the data (command) from the memory to the accumulator, etc., and then write the contents of the accumulator, etc. to the memory. Transfer content to an external device. In any case, the CPU needs to be involved, and the transfer requires a lot of glue.

Second, DMA (direct memory access) can be considered. In this case, a bus request signal is sent from the external device to the CPU as a control signal.

After the instruction cycle being executed, the CPU outputs a bus acknowledge signal and enters a holding state, and thereafter accesses the memory from the outside to [11] until the bus request signal is cleared. Data can be transferred directly between memory and external devices.

However, each address, data, control, and o-ib.

Since the bus becomes a two-state (high impedance) sum with respect to the CPU, the operation of the CPU itself also stops during this period. Therefore, when the CPU is busy executing a large number of instructions, it is necessary to perform this DMA frequently. is illegal.

Further, transferring a small amount of data using DMA is not preferable in terms of efficiency, as it requires an extra period of time KFil1 for sending a path request and sending a path acknowledgement, and it is rather preferable to transfer a small amount of data in an instruction cycle.

Further, when the CPU is in a holding state in DMA, time management becomes difficult.Even if an attempt is made to continue time management using a 0 interrupt, this interrupt itself is not possible in DMA. Furthermore, when a dynamo RAM (random access memory) is used as the memory, it is necessary to refresh the memory while also taking DMA into account, making the configuration even more complicated.

When controlling a VTR (video tape recorder) with many commands and statuses using the CPU,
There is a lot of arithmetic processing for control, and data transfer between the outside and the memory is also frequent. In this case, whether the external memory access is performed in instruction cycles or the DMA is performed at line 5,
KL, there are many problems with processing speed and software.

The present invention takes such circumstances into consideration, and the CPU
The object of the present invention is to provide a control device which allows the memory to be accessed directly from the KO section while the control device itself remains in operation.

In the present invention, in order to achieve such an objective, K.

The CPU is busy accessing memory from outside when it is not in a position to access memory.

Hereinafter, an embodiment in which the present invention/control device is applied to control a VTR and an editing machine will be explained with reference to FIGS. (Status and commands are transferred to and from 11, and the CPU performs arithmetic processing for controlling the VTR and editing machine.

FIG. 1 shows the control device of this example, in which the CPU
For example, 121 is an address terminal Ao as shown in FIG.
NAt! l, data terminal Do~D, control terminal Co~
C12, clock terminal, power supply terminal +5V.

It has a ground terminal QND. These children are connected to RAMII (RAMII), ROM (Read Only Memory) (31, etc.) through paths.Here, the data path is shown by a white arrow, and the address The data transfer between the CPU 12+ and the RAM+1 is controlled by the CPU data node (4)K. (2) in R, AM (1)
When addressing is performed, control is performed from the CPU address/(tufa(5)K).

On the other hand, the input/output port (6) is used for V'l, editing machine, and RAM (
It is used to transfer commands/statuses between 1M and 1M. Addressing at this time is performed by an address counter (7)K. This address counter (7) will be added later! # As mentioned above, the memory map “
FF80J ~ “FFgOJ (hexadecimal number, henceforth fif
Mr. l. ). Memory map allocation is performed by an address decoder (8). Here, R (JM (31) is designated as a program area, and RAM (11 is designated as a data area. In addition, data transfer between the input/output port 16) and RAM (11) is performed using the I10 data buffer (91). The addressing of RAM (1) by the address counter (7) is then controlled by the I10 address buffer (IGK).

As mentioned above, programs for controlling the VTR and editing machine are written in the KROM (31).

This program is executed in CP 012). Specifically, the program is executed by sequentially processing instruction cycles. This instruction cycle consists of one or more machine cycles. For example, when performing a load using direct addressing, the instruction cycle consists of one or more machine cycles.
z and M3 machine cycles are performed. in this case,
Ml is the command 7th cycle and MtlMs is the slave
This is a cycle in which the address to which the code is written is read from the ROM (3).

The instruction fetch cycle of M1 can be any instruction cycle. Since this is an instruction fetch, naturally ROM (3) is accessed, and RAM (1) is accessed.
1 is not accessed. In this example, this is 5KRAM.
(Considering that in any instruction cycle there is a machine cycle of Ml that does not access II, this M1
The cycle is used to transfer data between the VTR or editing machine and the RAM (1). This thing-
This will be explained in detail later.

The path control circuit aυ is connected to the CPU 121KJl via a control path. This bus control circuit αυ is a buffer (41 (5) (9) α・
KL so that the RAM (1) is accessed from the input/output port (6) side at the timing of the machine cycle M1 mentioned above, and at other timings, the CPU 1
I am using 5K so that I can access RAM III from the 23rd side.

That is, the M1 machine cycle consists of four clocks in the states TI, T2, T8, and T4 (1 and 4 in Figure A).
), the content (OP code) from the program counter of CPU +21 is transferred to the address bus, and the 7 retrieval address is transferred from Ts to T4 states (Fig. 4A). The address is originally for addressing the lower 7 bits of the diode memory for refreshing. t
In addition, one active low signal is sent from the T1 state to the single state in this M1 machine cycle,
Indicates that this machine cycle is an instruction fetch cycle (see Figure 4B). Also, the memory request signal M
REQ and read signals RD are sent out as shown in FIG. 4C and D. In addition, the memory request signal MREQ
Refresh signal RFSH is synchronized with K from T3 to T4.
(Figure 2 to 4 F), which means that the fresh address is sent out over the lower seven states of the address bus.
In this example, among these control signals, the M1 signal and the clock CLK are used, that is, they are ANDed to obtain the transfer timing for the VTR. (Fig. 4H). On the other hand, the transfer timing for the editing machine is obtained by ANDing the S7 retrieval signal RF8H and the clock CLK (Fig. II 4).

Further, as shown in FIG. 4G, the address counter (7) transfers data for addressing VTRK-related data at the active low timing of the refresh signal RF8H (FIG. 4F), and on the other hand, the Data for seven dressings of data related to the editing machine is transferred at four timings. As a result, R1 is
, Wl, the data transfer of the editing machine is performed. That is, at the timing indicated by Wl, the address for writing the status from the editing machine is transferred, and at the timing indicated by R1, the address for reading the command to the editing machine is specified. Note that the timings of R1 and Wl are alternately performed twice each time, but of course it may be once per time, but in this example, the timing is only 15 times, which is alternately performed for timing formation.

Similarly, the stator of 1VTR is performed at the timing of W2,
Commands are supplied to the VTR through the R2 tie.

In this case, Wt K oite)t "FFFFJ ~"F
'FEOJ is cracked, and at the timing of R1, [F
FDPJ ~ [F F COJ is allocated. Also,
The timing of Wz is “F F B FJ~”FF person 0
” was cracked and the timing of R2 was [FFQFJ~
"FF80J is being hacked.

When this configuration is busy, the CPU 121 executes arithmetic processing for controlling the VTR and editing machine. That is, each instruction cycle is executed continuously.

On the other hand, the status information from the VTR and editing machine is transferred to the RAM (II Memo 1) via the input/output port (6) and I10 data path (9). In this case, as shown in FIG. 4, this write is performed at a timing when KCPU+21 does not access RAM (1), so it does not cause any inconvenience to the instruction cycle of CPU (i).
At a predetermined timing of the machine cycle, the I10 data bus buffer (9) is turned on, while the CPU 1211
11') Data bus buffer (4 has 2 states).

After the status from the VTR is written into the RAM +11k, the CPU 12+ executes a desired operation thereon. And the resulting command is RAM
(L's memory area "PFQFJ~"F'F80J
I am sorry to write K. And this command is the input/output port (
6) is output to VTRK.

Similarly, the same control is performed on the editing machine, and in this case, the memory area "FFFFJ -1"FFC0
Use J key. In addition, I10 address bus buffer α
- is turned on at the same timing as the l10f-terbus buffer, and becomes two states with the same timing as the address bus buffer (4) on the reverse KCPU 12J side (data bus buffer (4) on the 514 CPU side).

In this way, no change is made to the operation of the CPU 121, in other words, the CPU 121 continues the instruction cycle while the RAM+11 is set up so that it can be accessed from the VTR or editing machine, so data is transferred extremely quickly. input/output, and there is no problem with the software.

No, this example's CPUt2re)tfa2 figure and r)'IE
As shown in Figure 4, there is a refresh address that specifies the lower 7 bits of the address bus for dynamic memory refresh! [It is sent at the timing shown in Figure 4 PK. Therefore, it is a good idea to use the fresh address for @==-4VTR data transfer addressing, and use the transfer address from the editing machine to perform data transfer addressing for the editing machine. You can also do it like this′
f'', the address counter ('I> can be omitted. If the refresh address is used for addressing data transfer related to VTFL1, R
It is preferable that at least a part of the RAM (11) be static RAM.

As mentioned above, the present invention control f! According to @, CPU
For example, when M is not accessing memory,
KL-(KL) is installed in the first memory so that ttKRAM can be accessed by an external device.

And even the case with the CPU in the operating state is busy so that data can be transferred between the external device and the RAM without being put into a hold state, for example.

Therefore, more control can be performed more quickly by effectively utilizing the CPU and RAM. Moreover, since the CPU itself is not affected by the delta transfer between the external device and the memory, the degree of freedom in terms of software is increased.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.
By providing a plurality of CPUs for one data area and allowing these CPUs to access the data area exclusively, the memory area can be shared without reducing the processing speed of each CPU. It is also possible to share the program area instead of sharing the data area. In such a case, the bus control rules become a little complicated, but for example, if the CPU is
All you have to do is do something like

[Brief explanation of the drawing]

FIG. 1 is a pull diagram showing one embodiment of the control device of the present invention, FIG. 2 is a schematic plan view for explaining FIG. 1, and FIG.
The figure and 4th WJ are time charts for explaining the embodiment of FIG. 1. (1) is RAM, (2) is CPU, (4) is CPU data bus buffer, (5) is CPU address bus buffer, (6) is human output port, (9) is I10 data bus buffer, (11I is I10 address bus buffer,
αυ is a bus control circuit. 31st! ! ! 1

Claims (1)

[Claims] a storage device and at least 41 devices accessing the storage device;
A control device comprising: a central processing unit; and a circuit unit that accesses the storage device at a timing when the central processing unit is not accessing the memory.