JPH031264A - Multi-processor system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time by transferring data from an access origin module to a local memory of the processor module concerned, when a coincidence detection is executed by a multicast address coincidence detecting means and a broad-case address coincidence detecting means. CONSTITUTION:In a processor module, in the case an input address coincides with a multicast address and a broadcast address by a multicast address coinci dence detecting means 202 and 9 broadcast address coincidence detecting means 201, data from an access origin module can be inputted to a local memory of the processor module. Accordingly, the data can be transferred simultaneously to many processor modules from the access origin module. In such a way, the data transfer time (loading time) can be shortened without being influenced by the number of sets of the processor module, the kinds of data to be trans ferred and the kind of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides data transfer from the access source module to the processor module, in which a plurality of processor modules each having a built-in local memory and an access source module are connected to a shared bus. This invention relates to a multiprocessor system that performs.

(Prior Art) Figure 2 is a block diagram of a multiprocessor system to which the present invention is applied. In the figure, a main processor module 1, a shared memory module 2, a secondary storage module 3 such as a magnetic disk, and a plurality of input/output units (hereinafter referred to as Il
It's called o. ) Processor modules 4-1 to 4-n are connected to a shared bus 5. Here, main processor module 1. Although the figure shows a case where one each of the shared memory module 2 and the secondary storage module 3 is connected, a plurality of these modules may be connected.

FIG. 3 shows an example of the internal configuration of the I10 processor module shown in FIG. 2, and shows the case of a communication control module.

In FIG. 3, the I10 processor module 4-1 (
Hereinafter, i=1.2. ..., n. ) is a microprocessor 41i that controls the I10 processor module itself as a communication control module, a local memory 42-1 that stores programs, transmitted and received data, and control information of the microprocessor 41-1, and a local memory 42-1. A DMA controller (hereinafter referred to as a DMA controller) that performs DMA transfer with the shared memory 2 (shown in Figure 2).
It's called C. ) 43-i and a bus interface control unit 44-1 that controls the interface with the shared bus 5.
, a line control unit 45-1 that performs line control such as serial/parallel conversion, modem signal monitoring, and transmission, and these microprocessors 41i and local memory 42-1.
and DMAC43-1 and bus interface control section 44-
1 and an internal bus 46-1 that connects the line control section 45-1.

Here, the local memory 42-1 includes the microprocessor 41-i in the I10 processor module 4-i and D
It is accessed from the MAC 43-i, and the shared bus 5
．． Bus interface control unit 44-1 and internal bus 46
-1 to other modules.

FIG. 4 is an explanatory diagram showing the conventional allocation of address spaces on the shared bus 5. As can be seen from the figure, the shared memory of the shared memory module 2 and the local memories 42-1 to 42 of each I10 processor module 4-1 to 4-n.
Different addresses are assigned to 2-n (hereinafter also referred to as LMI to LMn).

FIG. 5 shows the I10 processor module 4-i of FIG.
FIG. 2 is a block configuration diagram showing a conventional example of a bus interface control section 44-1 of FIG.

The address signal on the shared bus 5 is input to the address-number output circuit 101 of each I10 processor module 4-i (i=1, 2.-", n). In this address-number output circuit lot, , checks whether the address signal is an address assigned to its own local memory 42-1.Then, the address-number construction circuit +01 checks if the address signal matches the address assigned to its own local memory 42-1. The timing control circuit 102 is activated by the output of the address-number configuration circuit 101.The address conversion circuit 103 and the data buffer 104 are activated by the output of the timing control circuit 102.This causes the address conversion circuit +03 and the data buffer 104 to be activated. Buffer 104
．． Local memory 42-i via internal bus 46-1
(FIG. 2) is accessed. Here, the address conversion circuit 103 converts the local memory 42-4 on the shared bus 5 into
2-1 (L) (FIG. 4) and the address mapping of the local memory 42-1 on the internal bus 46-1.

The DMAC 43-i (FIG. 3) connects other memories on the shared bus 5 (the shared memory of the shared memory module 2 and other I1
0 processor module local memory), the timing control circuit +02 is activated and the shared bus 5 is accessed via the address register 105 and data buffer 104.

In addition, a write register 106 and a read register 107
is main processor module 1 (Figure 2) and I10
Microprocessor 4 in processor module 4-i
1-i. Here, the write register 106 transfers information from the main processor module 1 to the microprocessor 41-1 (main processor module 1 writes, microprocessor 41-1 reads), and vice versa. This is the read register 107. These write registers +06 and read registers 107
is controlled by a timing control circuit 102.

In the system described above, a method of IPL (initial program loading) to each of the I10 processor modules 4-1 to 4-4 is shown in FIGS. 6 and 7. Note that the program a stored in the secondary storage module (here, the case of a magnetic disk module is shown) 3 is transferred to the I10 processor modules 4-1 to 4-
(n-1) local memory 42-1 to 42- (n-
1), program b to I10 processor module 4
A case will be described taking as an example the case where the data is loaded into the local memory 42-n of the data 42-n.

First, the first method of IPL is to transfer the program of the magnetic disk module 3 to the I10 processor module 4-1 using the built-in DMAC (not shown) of the magnetic disk module 3, as shown in FIG. 6(a). ~4-local memories 42-1 to 42-Loge are loaded. Therefore, in the illustrated example, program a is transferred from the memory area 31 of the magnetic disk module 3 to the local memories 42-1 to 42- (row 1), and program b is transferred from the memory area 32 of the magnetic disk module 3 to the local memory 42-n. IP
As shown in FIG. 6(b), the L time is TXn, where T is the loading time for each I10 processor module. Note that DMA■ indicates the loading time from the magnetic disk module 3 to the local memory 42-1 of the I10 processor module 4-i using DMAC.

Next, the second method of IPL is to transfer the DMA from the magnetic disk module 3 to the shared memory of the shared memory module 2 using the built-in DMAC of the magnetic disk module 3, as shown in FIG. Then, the shared memory is loaded into the local memories 42-1 to 42-n of the I10 processor modules 4-1 to 4-n. In this method, each I10 processor module 4-1 to 4-n has a DMAC 43-1 to 43-n, respectively.
has a mouth Therefore, in the illustrated example, FIG. 7(a)
As shown in the figure, the memory area 3 of the magnetic disk module 3
Programs a and b are sequentially transferred by DMA from 1 to the memory areas 21 and 22 of the shared memory of the shared memory module 2 (in this case, the transfer time is DMA2, respectively).

Indicated by DMA ■. ). When program b is DMA-transferred from the magnetic disk module 3 to the memory area 22 of the shared memory of the shared memory module 2, at the same time, the program a is transferred from the memory area 21 of the shared memory to the I10 processor modules 4-1 to 4- (n- 1) Loading the local memories 42-1 to 42-(n-1) (in this case, the loading time is DMA■,
DMA ■, . . . ). Thereafter, program b is loaded from the memory area 22 of the shared memory into the local memory 42- of the I10 processor module 4-b. This method is effective when loading the same program into multiple I10 processor modules because the same program can be loaded into multiple I10 processor modules simultaneously from the shared memory.

(Problems to be solved by the invention) 1. ,.

However, the above-described IPL method had the following drawbacks.

(1) In the first method of IPL, from the magnetic disk module 3 to the individual I10 processor modules 4-1 to 4
- To load programs sequentially for n,
As shown in FIG. 6(b), the time (IPL time) until loading of all I10 processor modules 4-1 to 4-n is completed is TXn (here,
Loading time for T knee I10 processor modules, n: number of I10 processor modules)
It is given by , and is proportional to the number n of I10 processor modules. Therefore, the number n of I10 processor modules
If there is a large number of IPL times, there is a drawback that the IPL time increases.

(2) Furthermore, in the second IPL method, as the number of types of programs to be transferred increases, the time (IPL time) required to complete loading of all (1)10 processor modules also increases.

In particular, compared to the first method, the second method requires more time to transfer the program to the shared memory of the shared memory module 2. Therefore, when the program to be loaded is different for each I10 processor module, This method has the disadvantage of requiring more loading time (IPL time) than the first method.

Although the above description has been made for the case of IPL, the same can be said for general data transfer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multiprocessor system in which data transfer time (loading time) can be shortened without being affected by the number of processor modules or the types of data and programs to be transferred. be.

(Means for Solving the Problems) According to the present invention, a plurality of processor modules each having a built-in local memory and an access source module having data to be loaded are connected to a shared bus, and the access source module is connected to the multiprocessor module. In the system for transferring data to the local memory of the processor module, each of the processor modules includes multicast address matching detection means for detecting a match between an input address and a multicast address indicating a group to which the local memory of the processor module belongs; Broadcast address matching detection means for detecting a match between a broadcast address by which the local memory of all the processor modules is accessed and a manual address, and when a match is detected by the multicast address matching detection means or the broadcast address matching detection means. , the data from the access source module is transferred to the local memory of the corresponding processor module.

(Function) Therefore, in the processor module, when the input address matches the multicast address or broadcast address by the multicast address match detection means or the broadcast address match detection means, data from the access source module can be taken into the local memory of the processor module. I can do it.

Therefore, data can be transferred from the accessing module to many processor modules at the same time.
The data transfer time (
Loading time) can be reduced.

(Example) Next, embodiments of the present invention will be described using the drawings.

First, FIG. 2 is a block diagram showing an example of a multiprocessor system to which the present invention is applied, and FIG. 3 is a block diagram showing an example of the internal structure of the I10 processor module in FIG. 2. Since FIG. 3 has been described above, its explanation will be omitted.

FIG. 1 is a block diagram showing an embodiment of the present invention of the bus interface control section 44-1 shown in FIG. In addition, the first
In the figure, the same reference numerals are used for the same parts or parts having the same functions as in FIG. 5.

Before explaining FIG. 1, FIG. 8 will be explained.

FIG. 8 is a diagram showing address space allocation on the shared bus 5 in the present invention. In the figure, the broadcast address refers to the local memories 42-1 to 42-n of all I10 processor modules 4-1 to 4-n.
This is the address of the area accessible to all the local memories 42-1 to 42-n (L
M 1 to L M n ) are allocated to the same area in the address space of the shared bus 5. A multicast address is an address of an area that can access the local memory of all I10 processor modules belonging to a group based on the group number when I10 processor modules are divided into a plurality of groups. In the example of FIG. 8, L'MI and LM2 are assigned to multicast address 1, and LMn is assigned to multicast address 2.

Note that in both the broadcast address and multicast address areas, only write operations to the local memory (LM) of the corresponding I10 processor module are allowed, and read operations are not allowed.

In the example of FIG. 8, the address space of the shared bus 5 is
6MB, each I10 processor module 4-1 to 4
-n local memories 42-1 to 42-n (LM1 to L
The address space of Mn) is 1M byte, and the shared memory area 1 individual address area (individual L
Although the allocation is made in this order: M1=LMn address area), multicast address area, and broadcast address area, the present invention is not necessarily limited to such an allocation.

Next, the broadcast address-multiple output circuit 201 and the multicast address-multiple output circuit 2 in FIG.
02 will be explained.

The broadcast address-multiple output circuit 201 compares the fixed bit pattern (broadcast address) with the address signal on the shared bus 5. In the address assignment example shown in FIG. 8, the broadcast address-multiple output circuit 201 compares addresses A23 to A20 (MS84 bits of the address line) to see if they are "'1111" (fixed bit pattern). When the address on the shared bus 5 is a broadcast address, the broadcast address-multiple output circuit 201 detects a match between the broadcast addresses, and outputs the detection output from the OR circuit 20.
4 to the AND circuit 205, where it is ANDed with the write instruction signal. That is, only during a write operation, the signal is supplied to the timing control circuit 102 through the OR circuit 206, and the timing control circuit 102 is activated.

The multicast address/multicast address output circuit 202 compares the output of the group address register 203 (the group address of its own I10 processor module) with the address signal on the shared bus 5. In the example of address assignment in FIG. 8, regarding the I10 processor module 1 (LMI), a group number "E" (1110) is written in the group address register 203 in advance. Therefore, multicast address - several output circuit 202
In this case, addresses A23 to A2° on the shared bus 5 are “111”.
0'', a match is made and the timing control circuit 102 is activated as in the case of the broadcast address described above, and a write operation is performed to the local memory.

Note that the other input terminal of the OR circuit 206 is connected to the individual address -
Multiple sheet output circuit 101 (address mentioned above - several sheet output circuit 10
It is the same as 1. ) is connected to the output end of the

Next, the operation of the timing control circuit 102 will be explained using FIG. 9. Note that FIG. 9 is a time chart showing an example of the operation of the timing control circuit 102 in FIG. 1.

Addresses, write data, and write signals are transmitted from the shared bus 5 to the bus interface control unit 44-1 as shown in FIG.
It is supplied as shown in a) to (c).

When an address-number output signal is outputted from the broadcast address-number output circuit 201 or the multicast address-number output circuit 202, for example, from the multicast address-number output circuit 202 as shown in FIG. , the timing control circuit 102 turns on the ready signal on the shared bus 5, which is a control signal, as shown in FIG. Note that by activating the timing control circuit +02, the address conversion circuit +03 and data buffer 1
04 etc. are activated.

Next, from the shared bus 5, the I10 processor module 4-
The internal bus 46-1 is acquired via the bus interface control unit 44-1 in i, and the local memory 42-1 is accessed (FIG. 3). That is, local memory (L
M) 42-i address (LM address), data (L
M write data) and write pulses (LM write signal) are sent from the shared bus 5 to the bus interface control unit 44-i,
It is supplied to local memory 42-1 via internal bus 46-1. In this case, the bus interface control unit 44
-1, the LM address is the address conversion circuit 103
The LM write data is supplied to the internal bus 46-i (the control bus is not shown) via the data buffer 104, and the LM write signal is supplied via the control signal line and timing control circuit +02.

However, the internal bus 46-i is connected to the microprocessor 41-i.
The time it takes to acquire the internal bus 46-1 varies from access to access and from I10 processor module to I10 processor module.

Next, when the write operation to the local memory 42-i is completed, the LM ready signal shown in FIG. 9(h) is transmitted from the local memory 42-1 to the internal bus (control bus) 46-i.
The signal is sent to the timing control circuit 102 via. As a result, the timing control circuit 102 turns off the ready signal on the shared bus 5 as shown in FIG. complete access.

The ready signals on the shared bus 5 form a wired OR as shown in FIG. That is, when a plurality of I10 processor modules connected to the shared bus 5 are activated, the ready signal is turned off in synchronization with the I10 processor module that returned the ready signal the latest.

Next, the module from which the local memory of the I10 processor module is accessed, here the magnetic disk module 3, detects the change of the ready signal from on to off, completes the access to the local memory, and
address above.

Stop sending data and write signals [(a) to ((a) in the same figure)
c)], thereby the address-number configuration signal in the I10 processor module is stopped [FIG. 4(d)], and the timing control circuit 102 completes a series of operations.

Here, FIG. 1O will be briefly explained. FIG. 1O is an explanatory diagram of the wired-OR formation of the ready signal on the shared bus 5 and the detection of the access completion signal in the access source module (here, the magnetic disk module 3).

In the figure, the transistor 6 in the timing control circuit 102 of the bus interface control unit 44-i of each I10 processor module 4-i is turned on (in this case, the transistor 6 of any one I10 processor module is turned on). As a result, the ready signal is turned on, and I10, which turns off the transistor 6 at the latest, turns on.
The ready signal is turned off in synchronization with the processor module.

Furthermore, detection of an access completion signal in the access source module (magnetic disk module 3) will be explained. 7
．． 8 is a D-type flip-flop, and 9 is an AND circuit.

When the ready signal is turned on, the output Q of the D-type flip-flop 7 becomes logic "0°" and is input to one side of the AND circuit 9. At this time, the output of the D-type flip-flop 8 is input to the other input of the AND circuit 9. σ is logic "1". Therefore, the output of the AND circuit 9 becomes logic "0".Next, when the ready signal turns off, the output Q of the D-type flip-flop 7 becomes logic "1", and the output of the AND circuit 9 becomes logic "1". The output of the D-type flip-flop 7 becomes logic "1". Next, the output q of the D-type flip-flop 8 is inverted by the clock signal, and the output of the AND circuit 9 becomes logic "0". A rising edge detection circuit consisting of an AND circuit 9 detects a change in the ready signal from on to off, and obtains an access completion signal to the local memory.

Next, the IPL operation of the present invention will be explained using FIG. 11. The main processor 1 is a bus interface controller 44 of each of the 10 processor modules 4-1 to 4-n.
-1 to 44-n group address register 203 (
1) (not shown in FIG. 11), write the group number to the DM built in the magnetic disk module 3.
The AC is used to perform DMA transfer to the multicast address space.

For example, program a in memory area 31 is transferred to multicast address 1. As a result, the local memories (LMI and LM2 in the example of FIG. 8) assigned to the multicast address 1 are simultaneously written. Next, the memory area 32 of the magnetic disk module 3
Program b is transferred using the DMAC built in the magnetic disk module 3 in the conventional DMA transfer. Note that the writing operation of the I10 processor module to the local memory using the multicast address is as described above.

In this way, as shown in FIG. 11(b), all IPLs are completed by transferring as many programs as there are types to be loaded from the magnetic disk module 3.

As can be seen from the above explanation, when loading the same program into multiple I10 processor modules,
Loading time (IPL time) can be shortened by performing IPL using a multicast address or a broadcast address. This IP
The effect of shortening the L time is of course superior to that of the first conventional method, but it also eliminates the need for DMA transfer to the shared memory of shared memory modules 1-2. This method is superior to the second method.

Further, even when loading different programs to all I10 processor modules, it can be done in the same amount of time as the first conventional method, and the drawbacks of the second conventional method are solved.

Furthermore, program a in FIG. 11(a).

The IPL time can be further reduced by transferring the common part of b (if necessary in all I10 processor modules) using a broadcast address (to all I10 processor modules). can.

Although the embodiment of IPL has been described above, the same can be said for general data transfer.

The present invention is not limited to this embodiment, and various applications and modifications can be considered without departing from the gist of the present invention.

(Effects of the Invention) As described above, by using the present invention, data can be transferred from an access source module to many processor modules at the same time. This brings about effects such as being able to shorten data transfer time (loading time) without having to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus interface control section according to the present invention, FIG. 2 is a diagram showing the configuration of a multiprocessor system to which the present invention is applied, and FIG. FIG. 4 is a block diagram showing an example of the internal configuration of a processor module; FIG. 4 is an explanatory diagram showing conventional allocation of address space on a shared bus; FIG. 5 is a block diagram showing a conventional example of the bus interface control section in FIG. 3. Diagram,
FIGS. 6 and 7 are explanatory diagrams showing the conventional IPL method for each I10 processor module, respectively. FIG. 8 is an explanatory diagram showing the allocation of the address space on the shared bus according to the present invention, and FIG. A time chart showing an example of the operation of the timing control circuit shown in FIG. 1, and FIG.
FIG. 11 is an explanatory diagram showing the detection of an access completion signal in the free disk module 3), and FIG. 11 is an explanatory diagram showing the IPL method according to the present invention. 3...2 o'clock memory module, 4-! ~4-n...I10 processor module, 5
...Shared bus, 42-1 to 42-n (LMI to LMn)...Local memory, 103...Address translation circuit, 104...Data buffer, 201...Broadcast address match detection circuit,
202...Multicast address match detection circuit, 2
03...Group address register. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 3: Resonance buff upper and rear space 1y1 dimensions are shown in Figure 4, Figure 6 (a), Figure 6 (b), Figure 7 (0)

Claims (1)

[Claims] A plurality of processor modules each having a built-in local memory and an access source module having data to be loaded are connected to a shared bus, and data transfer from the access source module to the local memory of the multiprocessor module is provided. In the system, each of the processor modules includes: multicast address matching detection means for detecting a match between an input address and a multicast address indicating a group to which the local memory of the own processor module belongs; broadcast address matching detection means for detecting a match between a broadcast address to be accessed and an input address, and when a match is detected by the multicast address matching detection means or the broadcast address matching detection means, the access source module A multiprocessor system characterized in that data is transferred to a local memory of a corresponding processor module.