JPS58123142A - Information processor - Google Patents

Abstract

PURPOSE:To increase the degree of freedom for production of a program, by providing an address space expanding circuit which is capable freely forming a program to an additional circuit which is used to expand the address space. CONSTITUTION:The output of an internal register 24 is fed to a buffer 25 through a data latch 14, and the operation given to a data latch 14 is controlled by two D F/F15 and 16. An additional address produced at a CPU data is transferred and set to the register 24 through a data bus 21. The F/F15 and 16 work by using a writing signal supplied to the register 24 and a signal 17 showing the reading start of an instruction given from the CPU as its clear input and clock input, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an improvement in its memory address @ structure.

As the functionality of information processing devices expands, the amount of required programs (number of instruction steps) increases, and the number of addresses that the address bus (for example, program counter) of information processing devices can originally create is no longer sufficient. . To compensate for this, attempts have been made to extend the accessible address space by increasing the word length per address by adding multiple bits in addition to the original address. .

The conventional address space expansion method was carried out by adding a circuit as shown in FIG.

This is a circuit for adding address bits to be added. The central processing unit creates address data to be added and once writes it into the internal register 4 through the data bus 1. Write control is performed by a write control signal transferred via the control bus 3. The address data loaded into the internal register 4 is immediately outputted to the address bus 2 through the buffer 5, and is added to the original address section to become an address for the storage device or peripheral device.

Figure 2 shows the structure of address information added to storage devices and peripheral devices; the original address information 6 from the central processing unit and the address information 7 added through the circuit of Figure 1.
are combined to obtain the actual address information ゛.8.

To explain the addressing operation, first assume that the address 6 from the central processing unit is 16 bits, and the address information 7 added by the circuit of FIG. 1 is 4 bits. Now, internal register 4 is 0 and address 6 from the central processing unit is 1000 (
Unless otherwise specified, the following values are expressed in hexadecimal. ) address, the address at that time is address 1000. Added address data Di- to internal register 4 at this address.
Suppose there is an order to go blue. The central processing unit is the third
In the figure, sequence 9 of instructions corresponding to internal register O is executed sequentially, and internal register 4 is executed at address 1000.
A write instruction 11 is executed. As a result, additional data D is immediately set in the internal register 4. However, the next address points to address 1001 in sequence 10 of this added address data D. That is, the third
Instruction 12 in the figure is the next instruction to be executed.

In this way, even if the address space can be expanded by adding additional address data, the next address to be specified will be the sequence of the added address data (for example, the memory chip specified by the added address data). )
is fixed at a specific address. This was a major obstacle in creating the program. In the case of examples, there is a constraint that the instruction to be executed after address extension must always be set at a fixed address.This is especially true because there is always only one type of instruction that can be executed after address extension. It means that.

The present invention aims to improve this drawback, and provides an information processing device having an address space expansion circuit that eliminates the restrictions imposed on programs by an additional circuit for expanding the address space, and allows programs to be freely created. Aim to make a fist.

The information processing device of the present invention includes a circuit for creating an additional address for address space expansion, and a circuit for changing the original address before adding the created additional address to the original address. Features.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit block diagram of the additional address transfer section in this embodiment, and the output of the internal register 24 is the data latch 1.
4 to buffer 25 through data latch 1
The latch operation for 4 is two D'F/I"15.16
It is configured to be controlled by many people. Additional address data created by a CPU (not shown) is transferred to and set in the internal register 24 via the data bus 21.

The two D-B'/B' operate by using the read-in signal inputted to the internal register 24 as its clear input, and using the signal 17 sent from the CPU indicating the start of reading an instruction as its clock input.

In a circuit with such a configuration, the central processing unit (C)'
When LJ) writes additional address data to the internal register 24, the F/f" 15.16 is reset, the data 2 bit 14 is latched, and the additional address data is written to the data latch. 14. Therefore, the data latch 14 retains the old data. When the central processing unit reads the next instruction,
Address data latched in data latch 14 is output to address bus 22 through buffer 25. This data is previous data. No address extensions or changes are made within this period. Therefore,
This period can be used to read and execute another instruction following the write instruction to the internal register 24. In this embodiment, D-F/F15 is set by reading K of the next instruction after the write instruction to the internal register 24, and furthermore, D-F/F15 is set at the start of reading of the next instruction.
F/F15 is set. As a result, the data latch 14 is unlatched, the internal register 24 is set, and additional address data is output to the address bus 22. Therefore, by executing an instruction to change the original address created by the central processing unit as the next instruction after the write instruction to the internal register 24, it is possible to arbitrarily determine the destination address after address expansion.

The addressing system in this embodiment will be described in detail below with reference to FIG. Assume a microprocessor with a 16-bit program counter. Memory access is possible using a total of 20 bits of address, with a 16-bit address created by the program counter as a lower address, 4-bit data created by the CPU as additional address data, and an upper address.

Now, change the lower address to 1000. If the upper address is 0, address 1000 of memory space (A) is specified. By setting an instruction to set the upper address to 3 at this address, data 3 is set in the register 24 of FIG. However, this data 3 is not immediately combined with the lower address (1001 in this case),
It is not appended to the lower address until the processor executes the next instruction. This control is performed by the data latch 14 in FIG.
and DF/F15,16.

Therefore, the instruction to change the lower address (1001) to (1200) is set to the lower address (1001) of the memory space (A) as the next instruction to be executed by the process. As a result, the lower address is corrected to 1200, and then address 1200 of address space B specified by upper address 3 is addressed.

In this way, after changing the upper address, instead of immediately combining it with the lower address, the addresses can be combined after the instruction step to change the lower address to an arbitrary value, so the jump destination can be specified arbitrarily. can be set, increasing the degree of freedom in program creation.

In addition, a shift register may be provided to control the combination timing of the upper address and the lower address.

1;.

4. Brief explanation of the drawing
1. Figure 1 is a conventional additional circuit diagram for address space expansion, Figure 2 is a configuration diagram of address bits, Figure 3 is a memory diagram showing conventional addressing, and Figure 4 is an embodiment of the present invention. FIG. 5 is a memory diagram of the address change circuit according to the present invention.

1.21...Data bus%2,22...
... Address bus, 3.23 ... Control bus, 4.24 ... Internal register for address extension %5, 25 ... Output buffer, 6 ...
...Original address information from the central processing unit, 7...
...Additional address information from additional circuit, 8...
...All address information in the information processing device, 9...
Old address space instructions, 10... New address space instructions, 11... Write instructions to internal registers, 12... Commands to be executed after changing registers. , 13...Data uyf control signal, 14...Data uyf, 15.16
...D type Furi, Pu Furo, Pu, 17...
...A signal indicating the start of reading instructions from the central processing unit.

Part f Leap Ichino 22 ~/z3 4th close (A) CB) 5th Leap

Claims (1)

[Claims] In an information processing device using an access signal having a plurality of bits as a unit address, a step of changing the upper bits of the unit address, and means for changing the lower bits of the unit address within a predetermined period after the change; An information processing apparatus characterized by comprising means for specifying an address by combining the changed upper bits and lower bits.