JPS63144696A - Bit phase synchronization system - Google Patents

Abstract

PURPOSE:To obtain an economical bit synchronization system by providing a delay part adjustable with an external signal, a part to produce a delayed information with a constant clock, information memories at every, combination of input and output lines, and a line switch part. CONSTITUTION:An output information to the switch part 2 varies its phase at every combination of an in-line 8 and an out-line 9 because of the uneveness of line lengths and elements in the switch part 2. In the delay part 3, a switched output 10 is delayed 101 with a phase difference of 1ns, the delayed information 101 is selected 102 by means of an output 12 from an internal control part to vary the delay amount at every combination of the lines for connection, and thus phases are made identical, and outputted 11. The output 11 is reproduced 9 by selecting 202 the output of an FF 201 at a time when a clock 16 is led. And the combination of the lines 8, 9 is stored in a memory 7. The internal control part 5 connects the switch 2 based on a signal from a main control part 6, and transmits the delayed information 12 based on an information in the memory 7 to the delay part 3. As a result, a delay amount calculation is not necessary at every connection, and accordingly the quantity hardwares is remarkably reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bit phase synchronization method in a communication path device of an exchange, and relates to a bit phase synchronization method for a communication path device of an exchange, and a bit phase synchronization method for performing phase adjustment and signal reproduction without providing a phase detection circuit or the like for each line. Regarding phase synchronization method.

[Conventional technology]

2. Description of the Related Art Conventionally, in communication path devices of exchanges, data input at different phases are reproduced according to the same clock, so it is necessary to adjust the phase of each input data. Regarding the bit phase synchronization method for this purpose, see 1.
986, Collected Papers of the International Cölich Seminar Φ on Digital Communication 9, c
a, 1-C4,4 (19B6, International
nal 7. urich 5gm1nar onDtg
ital Communion Collected Papers, C4,1-C
4, 4). In this conventional example, each line has an adjustable delay line (ad)'ustah1g delay 1ine as shown in FIG.
), phase detector
, a control circuit (control logic) is provided,
The amount of data delay is adjusted and signal reproduction is performed according to the reference clock.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology requires a phase detection circuit and a control circuit for each line, which has the problem of increasing the amount of hardware.

An object of the present invention is to provide an economical bit phase synchronization system that performs phase adjustment and reproduces signals without providing a phase detection circuit, a control circuit, etc. for each line.

[Means for solving problems]

The above purpose is to provide a delay section whose delay amount can be adjusted by an external control signal, a signal regeneration section which regenerates the data delayed by the delay section according to a fixed clock, and a signal regeneration section for each combination of a single line and an outgoing line. A memory section that stores delay amount data and sends the stored delay amount data to the delay section as an external control signal, a switch section that exchanges and connects the incoming line and the outgoing line, and a control section that controls the memory section. This is achieved by providing

[Effect]

The memory section stores in advance the optimum delay soak data for each connection combination of incoming and outgoing lines, and each time the control section controls the switch section to switch connections, the memory section also controls and responds accordingly. The delay amount data is sent as an external control signal to the delay unit provided in the line where the exchange connection was made, the delay amount of this delay unit is adjusted, the phase of the input data is adjusted, and the signal regeneration unit generates a constant clock. Perform signal regeneration according to the following.

In other words, if you store delay amount data for all connection combinations in advance and know the connection relationship between incoming and outgoing lines, you can immediately know the amount of delay, so there is no need to adjust the amount of delay for each connection. , No circuit is required for this purpose, and the amount of hardware can be significantly reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 is a block diagram of a switch LSI to which the present invention is applied and its external circuit, FIG. 2 is a block diagram of the delay section in FIG. 1, and FIG. 3 is a block diagram of the reproduction section in FIG. FIG. 4 is a block diagram showing a method of writing delay amount data, and FIG. 5 is a time chart explaining a phase detection operation.

In FIG. 1, a switch LSI 1 connects 52 inlet lines 8 and 52 outlet lines 9 in an exchange manner.

Reference numeral 2 denotes a switch unit, which is a space division type switch having 32×32 cross points, and exchanges data of 140 Mj/S. Reference numeral 3 denotes a delay section provided for each of the 32 switch section output lines 10, which adjusts the amount of delay of the output data of the switch section 2 based on an external control signal. Although the delay unit 3 is provided on the outgoing line side of the switch unit 2 here, it can be similarly implemented even if it is provided on the incoming line side. Reference numeral 4 denotes a reproducing section, which performs signal reproduction by latching input data at the rising edge of a clock. 7 is a memory circuit;
Delay amount data for all connection combinations of incoming line 8 and outgoing line 9 are stored. 6 is the main control circuit, switch LS
1 and the memory section 7. 5 is an internal control unit;
Based on the control signal from the main control circuit 6, the switch section 2. The delay unit 3 and the reproduction unit 4 are controlled, and the delay amount data from the memory circuit 7 is sent to the corresponding delay unit 3. 11 is a delay data line, 12 is a delay control line, 15 is a switch section control line, 14 is a connection control line, 15 is a delay amount data line, and 16 is a clock signal line.

Next, switch LS11 in FIG. The operation of the memory circuit 7 main control circuit 6 will be explained.

The phase of the data output from the switch section 2 differs for each connection combination of the input line 8 and the output line 9 due to the line length of the input line 8, the wiring length inside the switch section 2, and variations in elements. Therefore, data cannot be reproduced as is with the same clock. Therefore, the delay unit 3 changes the amount of delay for each connection combination to align the phases of each data, so that the reproducing unit 2 can latch the data at the center using the same clock. The data on the amount of delay and low data is based on the number of combinations of inlet aS and outgoing line 9, which is 10.
24 (32×52) are required and are stored in the memory circuit 7. When making an exchange connection, the main control circuit 6 sends a connection control signal to the switch LSI 1 and also sends a connection control signal to the memory circuit 7. The memory circuit 7 sends the corresponding delay amount data to the internal control section 5 of the switch LSI 1 via the delay amount data line 15 based on the connection control signal. The internal control section 5 controls the connection of the switch section 2 based on the connection control signal from the main control circuit 6, and also sends delay amount data to the corresponding delay section 3 via the delay control line 12.

The delay unit 3 to which the delay amount data is sent adjusts the amount of delay of the input data based on the data, and sends it to the reproduction unit 4 via the delay data line 11. The reproduction section 4 reproduces the data whose phase has been adjusted by the delay section 5 in accordance with the clock sent via the clock signal line 16.

Next, the internal structure and operation of the delay section 3 will be explained using FIG. 2. In FIG. 2, 101 is a delay circuit;
The data transmitted through the switch unit output line 10 is delayed by ins to generate eight pieces of delayed data with delay amounts from Qn and r to 7nJ. A selection circuit 102 selects one of the eight pieces of delay data based on the delay amount data. 103 is a register circuit, and the delay control line 12
The delay amount data sent through the memory is stored and sent to the selection circuit 102 as a selection control signal. 104 is a delay circuit output line, and there are eight Vc lines for each delay circuit. 105 is a selection control line.

The operation of the delay section 5 will be explained below. The delay amount data sent via the delay control line 12 is sent to the register circuit 103.
and is sent to the selection circuit 102 via the selection control line 105 as a selection control signal. In the selection circuit 102,
Based on this, one of the data transmitted through the eight delay circuit output lines 104 from the delay circuit 101 is selected. On the other hand, the delay circuit 10 is transmitted through the switch unit output line 10.
The data input to 1 is input from 01 to 7n by the delay circuit 101.
The signal is delayed by a phase difference of 1rLz up to z and sent to the delay circuit output line 104. Then, as described above, one of them is selected by the selection circuit 102 and sent to the delayed data line 11. As described above, the amount of delay of data from the switch section 2 can be adjusted by rewriting the storage contents of the register circuit 103.

Next, the internal structure and operation of the reproducing section 4 will be explained using FIG. 5. In FIG. 3, 201 is a flip-flop, which outputs input data at the rising edge of a clock. A selection circuit 202 outputs either the input data or the output of the flip-flop 201 based on a control signal sent from the internal control section 5 via the reproduction section control line 204. Normally, the output of the flip-flop 201 is selected, but when detecting the phase difference between the data and the clock in order to determine the optimal delay amount data to be written into the memory circuit 7, the output of the flip-flop 201 is selected to output the input data as is. Ru. 203 is a flip-flop output line.

The operation of the playback section 4 will be explained below. The winding of the normal exchange operation, the data and clock whose phase has been adjusted by the delay unit 5 are input to the flip 70 tube 201, and the data is transferred to the flip 70 tube output line 201 at the rising edge of the clock.
3, is selected by the selection circuit 202K, and is output to the output line 9. In this case, the phase of the data is evenly adjusted in the delay unit 3 so that the rising edge of the clock is at the center of the data bit waveform, so even if the data contains phase noise, it is possible to accurately reproduce the signal. It is.

When detecting the phase difference between data and clock, the reproducing unit 4
outputs the input data as is.

Next, a method of writing delay amount data to the memory circuit 7V will be explained using FIGS. 4 and 5. In Figure 4, 3
01 is a phase detection circuit that detects a phase difference between input data and a clock, calculates and outputs an optimal delay amount based on the phase difference. The phase difference is detected by measuring the time T from the rise of data to the rise of the clock, as shown in FIG. 502 is a delay amount data transfer line, and 303 is a phase detection fc control line. The operation will be explained below. First, the main control circuit 6 includes a switch LSI 1
and connects the incoming line 8 and outgoing line 9.

At this time, the data output to output@9 is selected by the selection circuit 202 shown in FIG.
This is not the data reproduced in step 1, but the data as it is received by the reproduction unit 41C. Next, the main control circuit 6 controls the phase detection device 301 via the phase detection device control line 303,
Instructs to detect the phase difference between data and clock. After detecting the phase difference, the phase detection device 301 calculates the optimum delay amount based on the data, and sends it to the memory circuit 7 via the delay amount data transfer line 302. The memory circuit 7 stores the received delay amount data at a predetermined address based on the connection control data from the main control circuit 6. Input the above operation to line 8
The optimal delay amounts for all connection combinations (1024 types) of the output line 9 and the output line 9 are stored.

In this embodiment, the switch LS11 does not require a phase detection circuit, a delay control circuit, etc. for each line, so the number of elements can be reduced, and power consumption can be reduced.

In addition, in the phase detection ff1t3ot, if a precise phase detection circuit is used, it is possible to accurately determine the amount of delay even when there is a lot of phase noise in the data, and it is possible to accurately reproduce the signal.

[Effects of the Invention] According to the present invention, since a phase detection circuit, a delay control circuit, etc. are not used for each line, the number of elements can be significantly reduced.

[Brief explanation of the drawing]

1 is a block diagram of a switch LSI to which the present invention is applied and its external circuit, FIG. 2 is a block diagram of the delay section in FIG. 1, FIG. 3 is a block diagram of the reproduction section in FIG. 1, and FIG. The figure is a configuration diagram showing how to write delay amount data.
FIG. 5 is a time chart explaining the phase detection operation. 1... Switch LSI, 2... Switch section, 3...
・Delay section, 4... Reproduction section, 5... Internal control section, 6.
...Main control circuit, 7...Memory circuit, 8...Input line, 9...Output line. 10... Switch unit output line, 11... Delay data line, 12... Delay control line, 15... Switch unit control line, 14... Connection control line, 15... Delay amount data line ,
1o1... Delay circuit, 102... Selection circuit, 103
...Register circuit, 1'Q4...Delay circuit output line,
105... Selection control line, 201... Free lug frog, 202... Selection circuit, 204... Flip 70
Tsubu output line, 204... Playback section control line, 301...
Phase detection device, 502... Delay amount data transfer line, 30
5... Phase detector control line.

Claims (1)

[Claims] 1. In a communication path device of an exchange, in a system in which signals are reproduced using the same clock from a plurality of data output from a switch unit that exchanges and connects an incoming line and an outgoing line, and each having a different phase, the input line of the switch unit A delay unit provided for each line or outgoing line and whose delay amount can be adjusted by an external control signal, and a signal regeneration unit provided for each outgoing line to reproduce the signal of data delayed by the delay unit according to a fixed clock. a memory unit that stores delay amount data for each connection combination of an incoming line and an outgoing line and sends the delay data to the delay unit as an external control signal; and a control unit that controls the switch unit and the memory unit. The delay amount data for each connection combination of an incoming line and an outgoing line is stored in advance in the memory part, and the control part controls the switch part, and each time a switching connection is made, the control part The unit controls the memory unit, sends the corresponding delay amount data as an external control signal to the delay unit provided in the line where the exchange connection is made, and adjusts the delay amount of the delay unit. Bit phase synchronization method.