JPH0512919B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to time division switches, and more particularly, to time division multiplexed input and output highways, each having a plurality of channels in one frame. The present invention relates to the structure of a time division switch which outputs an arbitrary channel of an arbitrary input highway to an arbitrary channel of an arbitrary output highway, and particularly relates to the structure of a frame synchronization circuit.

[Background of the invention]

Time-division multiplexed PCM transmission paths are widely used for switching, transmission, etc. For example, switching in a time division switch can be performed by exchanging time slots carrying voice or data between time division multiplexed PCM highways or on the same highway. A time division switch performs such exchange of time slots.

Normally PCM signals are transmitted bit serially,
Moreover, since multiple channels are temporally arranged on the same transmission line, in order to exchange time slots in a time division switch, the start position of the frame of each input highway must be set in the frame supplied to the time division switch. It must have a specific time relationship with the synchronization signal. In other words, frame synchronization must be achieved.

Conventionally, in order to achieve this frame synchronization, a buffer memory for channel phase adjustment and a buffer memory for frame phase adjustment have been required for each input highway. There is a "time division switching system" (Japanese Patent Application Laid-open No. 48-66707) which aims to reduce the memory and equipment by sharing this frame phase adjustment buffer memory with the storage means of the time division switch. This first synchronizes the channel phase of each input highway, then detects the phase difference between the frame phase of each input highway and the reference frame synchronization signal by the number of channel periods, and uses this to modify the write address of the storage means. By doing this, frame synchronization is achieved. According to this known configuration, frame synchronization can be achieved without using a frame phase adjustment buffer memory. However, in order to achieve channel phase synchronization and to detect the phase difference between the frame phase of each input highway and the reference frame synchronization signal, a frame synchronization signal detection circuit is required for each input highway. Since these are controlled separately, there is a drawback that the synchronization circuit device becomes large.

[Purpose of the invention]

An object of the present invention is to provide a time division switch that can control channel synchronization and frame synchronization simultaneously without using a frame synchronization detection circuit for each highway.

[Summary of the invention]

In order to achieve the above object, the present invention determines whether frame synchronization of each highway is achieved after multiplexing a plurality of input highways, and determines the phase control amount within one channel based on the result of this determination. Channel and frame synchronization is achieved by simultaneously controlling the modification amount of the write or read address of the storage means for storing digital information on the input highway.

[Embodiments of the invention]

Hereinafter, one embodiment of a time division switch embodying the present invention will be described with reference to FIGS. 1 to 4.

Figure 1 shows 8 with a bit rate of 8.192 Mb/s.
The configuration of a time division switch for switching between the input and output PCM highways is shown.
If one channel consists of 8 bits, each highway consists of 128 channels (channels 0 to 8).
127), and the interval of one frame is
It is 125μs (1/8kHz). Therefore, this time division switch is equivalent to a 1024×1024 grid switch.

In FIG. 1, 100 to 107 are input highways, 110 to 117 are 0 to 7 bit variable delay shift registers, 120 to 127 are shift registers for serial/parallel conversion, and 130 to 137 are the variable delay shift registers 110 to 117. 140-147 are shift registers for performing parallel-to-serial conversion and output phase adjustment between highways; 150-157 are output highways; 16
0 to 167 are synchronization control circuits corresponding to each highway, 171 is a multiplexer that sequentially selects and multiplexes signals from the eight highways, 172 is a latch that receives and holds the signal from multiplexer 171, and 173 is a circuit on the input highway. , speech memory that stores digital information for one frame, 1
74 is a latch for holding the output from the speech memory 173, 175 is a selector for selecting the address of the speech memory, 176 and 177 are latches for holding the address, 178 is a frame synchronization signal detection circuit, and 179 is its output. 180 is a subtracter for modifying the write address of the speech memory 173, 181 is a control memory that supplies the read address of the speech memory 173 and specifies channel switching;
182 and 183 are data buses and address buses for rewriting the contents of the control memory 181; 184 is a latch for holding information on the data bus; 185 is a selector for selecting the address of the control memory 181; 186 is a counter 192; A latch for holding the output, 187 a selector for sequentially selecting the counter outputs in the synchronous control circuits 160 to 167, and 188 a selector 18
189 is a match detection circuit that determines whether the upper 7 bits of latch 186 and the lower 7 bits of latch 188 match; 190 and 191 are latches for holding the output; 192 is a counter that defines the operation timing of each circuit in the time division switch, and 193 is a frame synchronization signal for controlling frame synchronization of the output highway.

In the above configuration, the block 10 enclosed by the dotted line constitutes the frame synchronization circuit of the present invention.

The operation as a time division switch will be briefly explained below, and then the operation of the frame synchronization circuit will be explained in detail. In Figure 1, each input highway 1
The multiplexed signals from 10, 111, . These outputs are each serial-parallel converter circuit 12
0, . speech memory 17
3 has a storage capacity of 1024 words to store digital information for one frame of 8 highways, and its write address is determined by the counter 192. The counter 192 has 10 bits, is counted up by the 8.192MHz clock _φ1 , and is counted up from 0 to 125μs at the time interval of one frame.
Changes up to 1023. When frame synchronization is established, the contents of the speech memory 173 are as shown in FIG. 2a. That is, address 8i+j (0≦
channel i of highway j (corresponding to INj in FIG. 1) is stored in j≦7). Also, since the output of the control memory 181 determines the read address of the speech memory 173,
Address 8i+j of control memory 181
By writing 8k+l (0≦l≦7) in (0≦j≦7), the digital information of the k-th channel of the input highway INl can be output to the i-channel of the output highway OUTj. Shift registers 140-147 parallel-serial convert the speech memory 173 output, and further correct the read-out time difference from the speech memory 173 between each highway to match the output timings of output highways OUT0-7. A specific value is loaded into the counter 192 using the 8KHz frame synchronization signal 193, and by changing this value, the time relationship between the frame start position of the output highways OUT0 to OUT7 and the frame synchronization signal can be changed. .

In actual operating conditions, the start point of each highway frame is input to the time division switch at different times due to delays caused by transmission lines and the like. Therefore, it is necessary to adjust this time lag to achieve frame synchronization. In order to achieve frame synchronization, it is necessary that a synchronization signal be inserted into the input signal. As the synchronization signal, a method of using specific bits within one frame, a method of inserting a synchronization pattern into a specific channel within one frame, etc. are realized. This embodiment shows a configuration using the latter. It is assumed that the synchronization pattern is placed on channel 0 of each input highway.

If frame synchronization is not achieved, the timing of writing to the speech memory 173 will be incorrect (writing will not be performed for each channel, but will span two channels), and as shown in FIG. Discrepancies occur in channel units. Hereinafter, according to Figure 1, the above 2
This section explains how to correct the misalignment and achieve frame synchronization. The counters in the synchronization control circuits 160 to 167 corresponding to each highway have 10 bits, and the upper 3 bits control the delay amount of the variable delay shift registers 110 to 117, and the lower 7 bits control the write address of the speech memory 173. Qualify. That is, the upper 3 bits correct the deviation in units of bits, and the lower 7 bits correct the deviation in units of channels. Here, for convenience of explanation, we will consider a state in which the deviation in bit units has been corrected. Coincidence detection circuit 18
9 compares the lower 7 bits of the counters in the synchronous control circuits 160 to 167 and the upper 7 bits of the counter 192, and if they match, it is high (hereinafter abbreviated as H).
Output the level. Meanwhile, synchronization detection circuit 178 detects whether the output of latch 172 matches the synchronization pattern. Synchronous control circuit 160-1
67 is when the output of the coincidence detection circuit 189 is "H",
Referring to the output of the synchronization detection circuit 178, if a synchronization pattern is detected, the counters 160 to 16
If the value of 7 is held as is and no synchronization pattern is detected, counters 160 to 167 are counted up. Now, assume that the deviation in channel units is as shown in FIG. 2b, and consider highway 0. As you can see from the figure,
Since channel 0 is delayed by one channel period, the lower 7 bits of the counter in the synchronization control circuit 160 stop at "0000001". Therefore, if this value is subtracted from the upper 7 bits of the counter 192 (if the result of subtraction is negative, the operation of MOD 128 is performed), and the write address of the speech memory 173 is set, then the contents of the speech memory 173 are As shown in Figure a, frame synchronization can be achieved. If synchronization cannot be achieved even after changing the lower 7 bits of the counters in the synchronization control circuits 160 to 167 from 0 to 127, it is because the writing timing to the speech memory is not synchronized with the start point of each channel, and the variable delay Shift register 110~
It is necessary to change the delay amount of 117. This amount of delay is controlled by the upper three bits of the counters in the synchronization control circuits 160-167, and varies within the range of 0-7 bits. Since one channel has 8 bits, synchronization can be achieved by adjusting the delay amount from 0 to 7 bits. Therefore, frame synchronization can be achieved using a 10-bit counter in addition to the 7-bit adjustment for each channel.

FIG. 3 is a time chart for explaining the timing of the circuit shown in FIG. 1. The time division switch operates using 8.192MHz two-phase clocks φ ₁ and φ ₂ as its basic clock. The counter 192 is counted up at the rising edge of _φ1 and changes from 0 to 1023. The multiplexer 171
Input highway IN using lower 3 bits of 92
Select 0 to 7 in sequence. From latch 172, the second
As shown in the figure, digital information of input highways 0 to 7 is output. The timing diagram in the lower half of Figure 3 shows only the portion for highway IN0 for clarity. The value of counter 192 is 8k
(k: integer), the control memory 181 is read using the output of the counter 192, and at the same time, in the frame synchronization circuit 10, one of the synchronization control circuits 160 corresponding to the input highway IN0 is read out.
Select one counter. Latch 130 holds the three most significant bits of latch 188 output to determine the amount of delay of variable delay shift register 110. on the other hand,
A subtracter 180 extracts a frame synchronization correction amount from the upper 7 bits of the latch 186 output.
A write address for the speech memory 173 is generated by subtracting the lower 7 bits of the 8 outputs. The synchronous control circuit 160 also includes latches 179, 190, 19
Using the outputs of the synchronization detection circuit 178 and the coincidence detection circuit 189 whose time has been adjusted in step 1, a count-up is performed if necessary. The operations described above are executed in a pipeline manner, and frame synchronization of all input highways can be achieved.

FIG. 4 shows the configuration of the synchronous control circuit 160 in FIG. 1 in more detail, and FIG. 5 shows the timing signal Si (0≦i≦7) used in FIG.
1 is a diagram showing the relationship between φ ₁ , φ ₂ , and the output of the counter 192. Further, FIG. 6 is a flowchart showing the operation of the synchronous control circuit.

In FIG. 4, 301 is the latch 191 in FIG.
The output becomes "H" level when a match is detected. Further, 302 is the output of the latch 179 in FIG. 1, which becomes "H" level when a synchronization pattern is detected. Furthermore, is 316 synchronized?
312 is a counter (ECNT) for forward and backward protection; 323 is a modification of the delay amount of the variable delay shift registers 110 to 117 in FIG. 1 and the write address of the speech memory 173; 10-bit counter (DCNT) that determines the amount, 31
8,319 is a flip-flop for detecting a carry from the lower 7 bits to the upper 3 bits of DCNT 323, and 306 is a flip-flop for detecting a carry when the carry occurs.
This is a flip-flop to prevent the DCNT 323 from counting up. flipflop 3
06, 316, and 318, S, R, and Q indicate a set input, a reset input, and a data output, respectively (RS flip-flop), and in flip-flop 319, CK, D, and Q indicate a clock input, a data input, and a data output, respectively.

The operation shown in FIG. 4 will be explained below with reference to FIG. In a synchronized state, the output of the SYNCFF 316 is at the "H" level, and if the synchronization detection 302 is at the "H" level when the coincidence detection 301 is at the "H" level, the ECNT 312 is reset. Synchronous detection 3
When 02 is at "L" level, the synchronization pattern cannot be detected, but in order to prevent synchronization from being lost due to bit errors due to transmission line noise, etc. (forward protection), ECNT312 is counted up.
When ECNT 312 reaches 4, it is assumed that synchronization has been lost and SYNCFF 316 is reset. In the out-of-synchronization state, if the synchronization detection 302 is “L” when the coincidence detection 301 is “H” level, the DCNT 323
count up. Here, when the DCNT323 is counted up, if there is a change in the upper 3 bits, the delay amount of the variable delay shift register changes.
PSFF30 because input digital information is destroyed
6 to inhibit operation of the synchronous control circuit after 8 clock intervals. The set signal of PSFF 306 is connected to AND gate 326 and flip-flop 319,
This can be generated by detecting in step 318 that the lower 7 bits of DCNT 323 are all "1" and that a count-up signal has been input to DCNT 323, and by taking S4 and AND 314. When synchronization detection 302 is at “H” level, ECNT312 is counted up, and when it reaches 4 (backward protection) SYNCFF31 is counted up.
6 to maintain synchronization. The synchronous control circuit in Fig. 4 corresponds to input highway IN0 and uses S1 to S4 as timing signals, but it is possible to shift these signals and use them (for example, use S2 to S5 for input highway IN1). Accordingly, a synchronous control circuit for input highways IN1 to IN7 can be configured.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control channel synchronization and frame synchronization simultaneously without using a frame synchronization circuit for each highway, and the hardware of the synchronization circuit can be significantly reduced. I can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the frame synchronization circuit according to the present invention, FIG. 2 is a diagram showing the contents of the speech memory, FIG. 3 is a diagram showing the operation timing of the circuit in FIG. 1, and FIG. FIG. 5 is a diagram showing details of the synchronous control circuit of FIG. 1, FIG. 5 is an explanatory diagram of timing signals used in FIG. 4, and FIG. 6 is a flowchart showing the operation of the circuit of FIG. 4.

Claims (1)

[Claims] 1. A plurality of input highways and a plurality of output highways each transmitting a frame signal including digital information of a plurality of time-division multiplexed channels; It has a storage means for storing in channel units, and a control means for controlling writing and reading of digital information to the storage means, and the digital information of any channel of any input highway is stored through the storage means. In a time division switch configured to output the signal to any channel of any output highway, the signal delay means provided for each of the above input highways and the digital information of the plurality of highways output from each of the above signal delay means are channeled. It has multiplexing means for multiplexing in units, and synchronization signal detection means for detecting a frame synchronization signal from the output signal of the multiplexing means, and the control means controls each input by the synchronization signal detection means. A time division switch characterized in that the signal delay amount of the signal delay means and the address for writing or reading digital information in the storage means are adjusted depending on the detection state of a highway synchronization signal. 2. The control means has means for storing the detection state of the synchronization signal by the synchronization signal detection means for each of the highways, and based on the state information, determines the signal delay amount of the signal delay means and the signal delay amount of the signal delay means. 2. The time division switch according to claim 1, wherein the address for writing or reading digital information into the storage means is adjusted to correspond to each highway. 3. The synchronization signal detection state storage means is composed of a counter with a predetermined number of bits provided corresponding to the highway, and each of the counters is configured to store the position of the synchronization signal of the highway detected by the synchronization signal detection means and the time division switch. A first group of bits for storing the phase difference between the reference position of the synchronization signal and the reference position as a counter value in units of channel periods, and a counter value for storing the period in which the synchronization signal is not detected on the highway in units of frame periods. and a second group of bits for storing digital information, and an address for writing or reading digital information in the storage means is adjusted for each channel according to the value indicated by the first bit group. . The time division switch according to claim 2, wherein the delay amount of the signal delay means is adjusted bit by bit in accordance with the value indicated by the second group of bits.