JP2000347833A - Ring buffer data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the ring buffer processor which can easily control a device, which stops input/output operation in synchronizing signal units, as an input/ output device. SOLUTION: A ring buffer 2 which buffers input data by temporarily storing the data is arranged between an input device previous-stage part and an output device trailing-stage part 3. The output of a comparator 7 is synchronized by the synchronizing signal osync from the output device trailing-stage part 3 to control the output device trailing-stage part 3 by using an EMPTY signal indicating that the storage capacity of the ring buffer 2 is EMPTY, thereby performing control so that input/output operation is stopped in units of synchronizing signals that the input device previous-stage part 1 and output device trailing-stage part 3 write.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer between an input device and an output device having different transfer speeds. The present invention relates to a ring buffer data processing device capable of operating at a data rate of.

[0002]

2. Description of the Related Art When data is transferred between an input device and an output device having different transfer speeds, a ring buffer data processing device arranges a storage device (ring buffer) between the devices to form an input device and an output device. Operation is possible at each data rate. Hereinafter, a conventional ring buffer data processing device will be described. FIG. 5 is a diagram showing an address configuration of a conventional ring buffer, FIG. 6 is a block diagram of the ring buffer control device, FIG. 7 is a detailed explanatory diagram of the input determining unit, and FIG. is there.

When data is transferred between an input device and an output device having different transfer speeds, a storage device (ring buffer) is arranged between the devices so that the data rate of the input device and the output device can be adjusted. This is a buffer control means configured to control the addresses of ordinary memories in a ring shape as shown in FIG. 5 so that the memory structure looks like a continuous memory structure.

A configuration of a conventional ring buffer when data is transferred between an input device and an output device will be described with reference to FIG. In the conventional data transfer between input / output devices, as shown in FIG. 6, the input device pre-stage unit 1 for outputting input data and the state of the ring buffer 23 are determined (write enable, write inhibit) and the input data is transferred to the ring buffer 2.
An input data control unit 22 for writing control (generating a write address / memory control signal) for the input device 3 and for indicating whether writing is possible or not for the input device pre-stage unit 1 and controlling the flow of data; a ring buffer 23 for temporarily storing data; Then, the state of the ring buffer 23 is determined (reading is permitted, reading is prohibited), the output data is read out from the ring buffer 23 (reading address / memory control signal generation), and the reading / non-reading is indicated to the output device rear stage 5 to read out. And an output device control unit 4 for reading data existing in the ring buffer in accordance with a control signal from the output data control unit 4.

Next, a conventional control method will be described according to an actual data flow. When the data transfer is permitted by the write permission signal from the input data control unit 22, the input device pre-stage unit 1 outputs the input data to the ring buffer 23, and the input determination unit 6 in the input data control unit 22 controls the ring buffer 23. The write enable / disable state is determined from the input data address output by itself and the output data address output by the output data control unit 4 in the state 23 (write enable / write disable).

At this time, the input judging unit 6 obtains a difference between the input data address and the output data address after Carry processing is performed on the input data address as shown in FIG. Judge whether the status is writable or not and output. In the writable state, the input data control unit 22 operates to increment the input data address in accordance with a data trigger signal (a signal indicating that data is valid) output from the input device front-end unit 1.

When the input judging section 6 in the input data control section 22 judges that writing is not possible, a write inhibit signal is output from the input data control section 22 to the input device front section 1 and this signal causes the data in the input device front section 1 to be output. The transfer stops and the write data is suppressed. On the other hand, the output device subsequent stage 5 determines the state of the ring buffer 23 (read permission,
Read prohibition) is determined based on the output data address output by itself and the input data address output by the input data control unit 22 to determine whether read is permitted or prohibited. At this time, the output determination unit 7 obtains the difference between the input data address and the output data address after Carry processing is performed on the input data address as shown in FIG. 8 and determines the storage capacity state of the ring buffer 23 from the result. Determines whether reading is possible or not and outputs it.

In the readable state, the output data control unit 4 increments the output data address in accordance with an output data trigger signal (signal indicating that it is in the data request state) output from the output unit rear part 5. Operate. When the output judging section 7 in the output data control section 4 judges that reading is not possible, a read inhibit signal is output from the output data control section 4 to the output device rear section 5, and the data request of the output device rear section 5 is inhibited by this signal. And the read operation is stopped.

[0009]

However, the above configuration is effective for an input / output device that performs input / output operation / stop for each data, but an input device and an output device are provided for each synchronization signal unit. When performing data transfer between devices that perform input / output operation / stop, there is a problem that a control method of an input data control unit and an output data control unit becomes complicated.

The present invention solves the above-mentioned conventional problems, and provides a ring buffer data processing device capable of easily controlling an input / output device which performs input / output operation / stop for each synchronization signal unit. The purpose is to do.

[0011]

SUMMARY OF THE INVENTION A ring buffer data processing device according to the present invention comprises an input device and an output device each having a unique data transfer rate and data unit, and an input device disposed between the input device and the output device. A ring buffer that temporarily stores and buffers data, a data number counter that is incremented by an input trigger of the ring buffer and decremented by an output trigger, and a full level of a storage amount of the data number counter and the ring buffer. A comparator that compares a specified full-level register and outputs a result; a comparator that compares the data number counter and an empty level register that specifies an empty level of the storage amount of the ring buffer and outputs a result; The output is a synchronization signal issync from the input device. FULL which indicates that the storage amount of the ring buffer is FULL by synchronizing Te
The write control of the input device is performed by using the signal, and the output of the comparator is output from the output device by the synchronization signal os
The output device is controlled using an EMPTY signal indicating that the storage amount of the ring buffer is EMPTY by synchronizing with the sync.

With this configuration, it is possible to realize a ring buffer data processing device that can easily control an input / output device that performs input / output operation / stop for each synchronization signal.

[0013]

The ring buffer data processing according to claim 1, wherein an input device and an output device each having a unique data transfer rate and data unit, and input data arranged between the input device and the output device. Buffer that temporarily stores and buffers the data, a data counter that is incremented by an input trigger of the ring buffer and decremented by an output trigger, and a full level of the storage amount of the data counter and the ring buffer is specified. A comparator that compares the data number counter and an empty level register that specifies an empty level of the storage amount of the ring buffer, and outputs a result.
By synchronizing the output of the comparator with a synchronization signal issync from the input device, the write control of the input device is performed using a FULL signal indicating that the storage amount of the ring buffer is FULL, The output is a synchronization signal osync from the output device.
, The output device is controlled using an EMPTY signal indicating that the storage amount of the ring buffer is EMPTY.

According to a second aspect of the present invention, in the ring buffer data processing device, the full-level register is set to {ring buffer capacity minus 1sync data amount} or less.
Data input operation / stop in units of isync is enabled.

The ring buffer data processing device according to claim 3, wherein the empty level register is $ 1osyn.
By setting the c data amount to｝ or more, data output operation / stop in osync units is enabled.

With the above configuration, it is possible to perform control such that input / output operation / stop is performed for each synchronization signal written by the input device and the output device.

An embodiment of the present invention will be described below.
FIG. 1 is a block diagram of a ring buffer control device according to an embodiment of the present invention, FIG. 2 is a diagram showing a memory map of the ring buffer, FIG.
Is a timing chart of the output operation.

The configuration of a ring buffer when data is transferred between an input device and an output device will be described with reference to FIG. As shown in FIG. 1, an input device front section 1 capable of performing an output operation / stop for a specific synchronization signal unit, a ring buffer 2 for temporarily storing data, and an output capable of performing an input operation / stop for a specific synchronization signal unit A data counter 4 that is incremented by an input trigger signal output from the input device front section 1 and decremented by an output trigger signal output from the output device output section 3; A full level register 9 for specifying the level, an empty level register 10 for specifying the empty level of the ring buffer 2, a comparator 6 for comparing the output of the data number counter 4 with the full level register 9 and outputting a magnitude relationship, and a comparator 6 is synchronized with an input synchronizing signal (issync) from the input device front-end unit 1 and a write control signal ( Flip-flop circuit 5 for generating a write permission / prohibition), a comparator 7 for comparing the output of the data number counter 4 with the empty level register 10 and outputting a magnitude relationship, and an output of the comparator 7 from the output device rear stage 3. Output synchronizing signal (osyn
The flip-flop circuit 8 synchronizes with c) to generate a read control signal (read permission / prohibition).

Next, a control method for solving the problem in accordance with an actual data flow will be described with reference to FIG. The input device front section 1 includes a flip-flop circuit 5
The write control signal indicating the write permission / prohibition state from the device is updated with its own synchronization signal (isync) (see the point A in the timing chart of FIG. 3). It outputs input data to the ring buffer 2 and simultaneously outputs an input data trigger signal.

The input data trigger signal enters the input address generator 12 in the ring buffer controller 11, updates (increments) the input data address, and the input data is written to the address of the ring buffer 2 output from the address generator. On the other hand, the input data trigger signal is also input to the data number counter 4 at the same time. The data number counter 4 operates so as to increment the counter in accordance with the input data trigger signal, and indicates the number of data currently stored in the ring buffer 2. The count number of the data number counter 4 is sent to the input part of the comparator 6, and the other input part of the comparator 6 receives a full level register 9 to which a numerical value that makes the number of data stored in the memory a full level is input. .

The comparator 6 compares the magnitudes of the two inputted numbers, and outputs a result indicating whether the current state of the number of storages in the ring buffer 2 is the FULL level or the non-FULL level. The output signal of the comparator 6, which is the status signal of the buffer 2, is input to the flip-flop circuit 5.

The input device pre-stage 1 receives a write control signal from the flip-flop circuit 5 indicating a write permission / prohibition state (see point B in the timing chart of FIG. 3). Data transfer is permitted by this write control signal output. Then, input data is output to the ring buffer 2 and an input data trigger signal is output at the same time. When data transfer is prohibited, the data output to the ring buffer 2 is stopped. By repeating the above operation, the input device front-stage unit 1 can easily perform the output operation / stop control for each synchronization signal.

On the other hand, the output device rear stage 3 updates the read control signal indicating the read permission / prohibition state from the flip-flop circuit 8 with its own synchronization signal (osync) (point C in the timing chart of FIG. 4). When the data transfer is permitted by this write control signal output, an output data trigger signal is output to the ring buffer 2.

The output data trigger signal updates (increments) the output data address of the output address generator 13 in the ring buffer controller 11, and the output data is read from the address of the ring buffer 2 output from the address generator. The output data trigger signal is also input to the data number counter 4 at the same time, and the data number counter 4 operates to decrement the counter in accordance with the output data trigger signal, and indicates the number of data currently stored in the ring buffer 2.

The count number of the data number counter 4 is sent to the input section of the comparator 7 and the other input section of the comparator 7 is provided with an empty level register 1 to which a numerical value which makes the number of data stored in the memory an empty level is given.
0 is input. The comparator 7 compares the magnitude relations of the two inputted numbers and outputs a result indicating whether the current storage number state of the ring buffer 2 is the EMPTY level or the non-EMPTY level. An output signal of the comparator 7 which is a state signal is input to a data input terminal of the flip-flop circuit 8.

The output device rear stage 3 outputs to the ring buffer 2 when data transfer is permitted by a read control signal (see point D in the timing chart of FIG. 4) indicating a read permission / prohibition state from the flip-flop circuit 8. A data trigger signal is output, and when data transfer is prohibited, data output from the ring buffer 2 is stopped. By repeating the above operation, the output device rear-stage unit 3 can easily control the output operation / stop for each unique synchronization signal.

[0027]

As described above, according to the present invention, data is transferred between an input device capable of inputting and stopping operation in units of a unique synchronization signal and an output device capable of inputting operation and stopping in units of a unique synchronization signal. In this case, it is possible to easily realize a control in which each data transfer operation / stop is controlled for each synchronization signal unit unique to the input device / output device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a ring buffer control device according to an embodiment of the present invention;

FIG. 2 is a diagram showing a memory map of a ring buffer according to the embodiment of the present invention;

FIG. 3 is an input operation timing chart according to the embodiment of the present invention;

FIG. 4 is an output operation timing chart according to the embodiment of the present invention;

FIG. 5 is a diagram showing an address configuration of a conventional ring buffer.

FIG. 6 is a block diagram of a conventional ring buffer control device.

FIG. 7 is a detailed explanatory diagram of a conventional input determination unit.

FIG. 8 is a detailed explanatory diagram of a conventional output determination unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input device front stage 2 Ring buffer 3 Output device rear stage 4 Data number counter 5,8 Flip-flop circuit 6,7 Comparator 9 Full level register 10 Empty level register

Claims (3)

[Claims] An input device and an output device each having a unique data transfer rate and data unit; a ring buffer disposed between the input device and the output device for temporarily storing and buffering input data; A data number counter that is incremented by an input trigger of a ring buffer and decremented by an output trigger, and a comparator that compares the data number counter with a full level register that specifies a full level of the storage amount of the ring buffer and outputs a result. A comparator that compares the data number counter with an empty level register that specifies an empty level of the storage amount of the ring buffer and outputs a result;
By synchronizing the output of the comparator with a synchronization signal issync from the input device, the write control of the input device is performed using a FULL signal indicating that the storage amount of the ring buffer is FULL, The output is a synchronization signal osync from the output device.
A ring buffer data processing device for controlling the output device using an EMPTY signal indicating that the storage amount of the ring buffer is EMPTY by synchronizing the data. 2. The ring buffer according to claim 1, wherein the full-level register is set to {ring buffer capacity minus 1sync data amount} or less to enable data input operation / stop in units of issync. Data processing device. 3. The empty level register stores $ 1os.
2. The ring buffer data processing device according to claim 1, wherein the data output operation / stop in the unit of osync is enabled by setting the amount of yn data to be equal to or more than｝.