JPS6061994A - Control circuit of dynamic memory - Google Patents

Abstract

PURPOSE:To prevent reduction of the processing speed of a data processor by performing a data refresh action of a memory block at the other side in the same memory cycle of the other memory block while an access is given to either one of even and odd memory blocks. CONSTITUTION:The least significant bit address 35 among addresses of an address bus 13 is set at level ''0'', and a row address strobe signal 19 given from a timing generating circuit 15 is lowered down to level ''0''. Under such conditions, memory blocks 24 and 25 of the ven side receive accesses to a request given from a processor 11 and perform the transfer of data with a data bus 14 via data buses 29 and 30. For memory blocks 26 and 27 of the odd side, an address which is designated by a refresh address address 75 is refreshed since the supply is inhibited for a column address strobe signal 39 by an NAND gate 34. When the address 35 is set at level ''1'', the data receives an access at blocks 26 and 27. Then the data is refreshed at blocks 24 and 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic memory provided in a data processing system, and more particularly to a control circuit for a dynamic memory that performs data refresh control.

[Technical background of the invention]

Conventionally, the refresh operation in a memory using dynamic memory cells involves preparing a counter circuit with a number of bits equal to the number of refresh cycles specific to the memory cell, and performing a refresh operation at a constant value based on the refresh address obtained as the count output of this counter circuit. A refresh cycle is inserted and executed every hour. When performing such a refresh operation, when a data access request occurs during the refresh cycle,
The device that outputs this access request, for example, either temporarily stops the microprocessor by sending a wait signal to the microprocessor, or detects the idle time of the microprocessor by observing the state of the microprocessor, and I'm trying to finish the refresh cycle. The latter method can make the presence of the refresh cycle more noticeable than the former method.

[Problems with background technology]

Among the conventional refresh control technologies, those that stop the microprocessor's operation using a wait signal to perform refresh in response to an access request from the microprocessor have a simple configuration, but they slow down the execution speed of the microprocessor. There is a drawback.

On the other hand, with a system that detects free time in a microprocessor and inserts a refresh cycle, it becomes difficult to detect free time because the processor itself accesses memory at high speed, and the circuit configuration is complicated. There is a drawback.

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to sacrifice memory cycles of a data processing device in order to refresh data in the memory in a data processing system equipped with a dynamic memory. In other words, it is an object of the present invention to provide a dynamic memory control circuit that does not reduce the execution speed of a data processing device and has a relatively simple circuit configuration.

[Summary of the invention]

Generally, in a data processing system equipped with a microprocessor, the microprocessor sequentially executes and consumes a group of instructions stored in advance in a memory. From the point of view of fetching instructions, this means that the unit increase in addresses is manipulated, and if the basic word length of the processor is used as a unit, the even or odd address changes alternately. However, there are cases in which the processor executes branch instructions, etc., such as consecutive accesses to odd addresses or instructions that require a long internal processing time, and no memory access occurs. However, the processor NoJ? Due to e-line processing and the separation of the execution unit inside the processor, such as the separation of the path control unit,
There are almost no cases where accesses to one of the odd addresses continue for a long time, or where no memory access occurs for a long time. Therefore, in a dynamic memory control circuit according to the present invention, in a data processing system equipped with a dynamic memory, this memory is divided into an odd address memory block and an even address memory block, and an independent A data access control circuit and a data refresh control circuit are provided, and either the even or odd memory block
When data is being accessed in response to a data access request from a microprocessor, which is a data processing device, the memory cycle time of dynamic memory can be reduced by refreshing the data of the other memory block in the same memory cycle. All of them can be used for five processors.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram when a dynamic memory control circuit according to the present invention is implemented in a microcomputer system.

In the figure, 11 is a micro 7'o setter in which one word of data to be handled and the bit width of the data bus are, for example, 16 bits, and the basic word length is 16 bits; 12, 1 .
9.14 are the control path, address bus, and data bus of this processor 11, respectively. Reference numeral 15 indicates an access request signal 16 from the processor 11 via the control path 12, and a refresh request signal 17 output from two fresh gourd request counters to be described later. A timing generation circuit that generates a refresh cycle signal 18, a row address strobe signal 19, a column address 6-trope signal 20, a write enable signal 21, an address selection signal 22, and a wait signal 23, respectively. be.

24 to 27 are memory blocks composed of dynamic memory cells, respectively, and constitute a dynamic memory 28 that stores addresses; one memory block 24 stores the upper 8 bits of an even address;
One memory block 25 stores the lower 8 bits of even addresses, one memory block 26 stores the upper 8 bits of odd addresses, and one memory block 27 stores the upper 8 bits of odd addresses.
stores the lower 8 bits of odd addresses. That is, this dynamic memory 28 divides the physical address space of the microprocessor 11 into its basic word length of 1.
It is divided into odd and even addresses in units of 6 bits, and further divided into upper and lower bytes, respectively. and the memory block 24 to 2
7 is the upper or lower byte data bus 29.30
The data bus 14 is coupled to the data bus 14 via the data bus 14 .

NOR gate 31.32 and NAND gate 33°3
The circuit consisting of 4 receives the address 35 of the least significant bit of the address transmitted on the address bus 13, the refresh cycle signal 18, and an inverted signal 37 of the column address strobe signal 20 by the inverter 36, and is connected to the even memory. It outputs a column address strobe signal 38 for blocks 24.25 and a column address strobe signal 39 for the odd memory blocks 26.2'i. Further, a circuit consisting of NAND gates 40 to 43 receives an upper byte selection signal 4 transmitted through the control path 12 for selecting an upper byte.
4. Output signals 45° 46 from the NOR gates 31 and 32 and an inverted signal 48 of the row address strobe signal 19 by the inverter 47 are input, and the row address strobe signal 49 and Row address strobe signal 50 for the upper byte memory block 26 on the odd number side
This outputs the following. Similarly, the circuit consisting of NAND gates 51 to 54 receives the lower byte selection signal 55 transmitted through the control bus 12 and for selecting the lower byte, and the signals 45, 46° 48, and selects the lower byte on the even number side. It outputs a row address strobe signal 56 for the memory block 25 and a row address strobe signal 57 for the memory block 27 of the lower byte on the odd number side. Note that the output signals 58 to 61 of the NAND gates 40.41 and 51.52 are as follows.
During the period when the signals 45 and 46 are at O level, the memory block 2
4 to 27 is used as a refresh request signal.

62 and 63 are address multigrazers for the even and odd side memory blocks 24, 25 and 26, 27, respectively, and when the signals 45, 46 are set to the O level, two refresh operations, which will be described later, are performed at 9-. The output from the counter is supplied as address 64.65 to the memory blocks 24 to 27, and in accordance with the level of the address selection signal 22, the upper 8 bits of the address 66 and the lower 8 bits transmitted on the address bus 13 are The address 61 is selectively supplied to the memory blocks 24 to 27 as the address 64.65.

68 and 69 are even-numbered memory blocks 24 and 69, respectively.
25, a refresh counter for odd-numbered memory blocks 26 and 27; Each refresh counter 6
B, 69 is the output signal 7 of the NOR gate 70 which receives the signal 45 and the row address strobe signal 19 as input.
1 and the above signal 46 and the row address strobe signal 19
The output signal 73 of the NOR gate 72 whose input is the count input signal, and the count output signal is the frequency address 74, 75 . ! : and is supplied to the address multiplexers 62 and 63.

Refresh request counters 10-76 and 77 sequentially count the oscillation output signals from the oscillation circuit 78, and output a refresh request signal 79.80 when a full count is reached. Refresh request signals from these two counters 76 and 77? 9. lJO is supplied to the timing generation circuit 15 as the refresh request signal 17 via the NOR gate 81. Furthermore, both of the above counters'
The signal 11.13 is inputted to 16.71 as a reset signal.

Further, each of the memory blocks 24 to 27 receives a write enable signal 2 generated by the timing generation circuit 15.
1 is supplied to each memory block 24 to 27.
The data write operation in is permitted when this signal 2 is set to 0 level.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG. First, an access request signal 1 is input from the microprocessor 11 to the timing generation circuit 15 via the control bus 12.
6 is lowered to 0 level. At this time, it is assumed that a refresh operation is being performed in every memory block in the dynamic memory 28, and the refresh cycle signal 18 generated by the timing generation circuit 15 is set to 0 level.

It is also assumed that when the access request signal 16 is lowered to the 0 level, the least significant bit address 35 of the address on the address bus 13 is set to the 0 level. That is, at this time, the addresses on the address bus 13 are even addresses. Now, since the least significant bit address 35 and the refresh cycle signal 18 are both at 0 level, the output signal 45-1 of the NOR gate 3 is
ts level and the output signal 46 of the NOR gate 32 are set to O level. This allows two NAND
One of the NAND gates 33 and 34 is opened, and the column address strobe signal 20 can be supplied as a signal 38 to the two memory blocks 24 and 25 of the upper and lower bytes on the even-numbered side. The above signal 45
is set to the level, thereby prohibiting the address multiplexer 62 from selecting the positive address 74 from the refresh counter 68. Furthermore, this address multiplexer 62 receives the address selection signal 22.
Based on the upper and lower 8 bits, the address of 66.61
is selected and supplied as address 64 to the two even-numbered memory blocks 24 and 25.

On the other hand, by setting the signal 46 to the θ level, the address multiplexer 63 selects the refresh address 75 from the Y refresh counter 69 and uses this as the address 65 for the two odd-numbered memory blocks 2.
Supply on 6.27. Therefore, the two even-numbered memory blocks 24.25 have addresses 66.6f! on the address bus 13! The two memory processors on the odd side, 26.1#, are addressed by the fresh address 751C from the refresh counter 69 (13-).

On the other hand, since the signal 46 is set to 0 level,
The refresh request signals 59 and 61 for the odd-numbered memory blocks 26 and 27, which are the output signals of the NAND game) 4J and 52, are both set to the level. Therefore, the row address strobe signal 50.57 obtained as the output signal of the NAND gate 43.54 can be supplied to the two odd-numbered memory blocks 26.27.

On the other hand, the row address strobe signals 49.56 for the two even-numbered memory blocks 24.25 are controlled in accordance with the upper byte selection signal 44 and the lower byte selection signal 55 from the processor 11, and are controlled in accordance with the upper byte selection signal 44 and the lower byte selection signal 55 from the processor 11. Or allowed for both bytes.

Next, in this state, when the row address strobe signal 19 from the timing generation circuit 15 is lowered to O level,
One or both of the two even-numbered memory blocks 24, 25 are normally accessed in response to a request from the processor 11, and the data bus 14-2 is accessed via the data bus 29, 31.
4 and receive and receive data. At this time, the write enable signal 21 is activated depending on the data write/read mode.
level is set. On the other hand, since the supply of the column address strobe signal 39 to the two odd-numbered memory blocks 26 and 22 is prohibited by the NAND gate 34, the address specified by the refresh address 75 is refreshed. Further, each time the row address strobe signal 19 is lowered to the O level, the output signal 73 of the NOR gate 72 is set to a level, and the refresh counter 69 sequentially counts this signal 73 to update the fresh address 75. Therefore, in the two odd-numbered memory blocks 26 and 27, a new address is refreshed every time the row address strobe signal 19 is lowered to the O level. Further, a refresh request counter 77 is reset by a signal 73 every time the refresh counter 69 counts up.

As a result, the output of the refresh request signal 80 is suppressed, and the counter 77 newly counts the oscillation output signal of the oscillation circuit 78 from the count 0 state.

In this way, the two even-numbered memory blocks 24.
When data is accessed in 25, the two odd-numbered memory blocks 26.2 are accessed in this memory cycle.
7 refreshes are performed. On the other hand, when the least significant bit address 35 is set to the level, contrary to the above, data is accessed in the two memory blocks 26 and 27 on the odd number side, and in the same memory cycle, data is accessed in the two memory blocks 26 and 27 on the even number side. Data freshening is performed in the two memory blocks 24 and 25 in the same manner as described above.

The access request from the processor 11 is stopped and the signal 16
is not activated for a predetermined period, and the refresh request counter 76
．． When at least one of the refresh request signals 79 and 77 is counted up and either one of the refresh request signals 79 and 80 is output, the refresh request signal 17 is input to the timing generation circuit 15. As a result, the refresh timing generating circuit 15 forcibly sets the refresh cycle signal 18 to the level. Then, the output signals 45 and 46 of the NOR gates 31 and 32 are both set to O level, thereby all the memory blocks 24 to 27 in the dynamic memory 28 are selected to the refresh state, and the signal 7
Refresh request counter 7 by 1.73!6.7
7 are reset at the same time. Then, after the refresh request counters 76 and 77 have counted up, the timing generation circuit 15 again forcibly sets the refresh cycle signal 18 to the level. Therefore, if there is no access request from the processor 11 for a long period of time, the different addresses of all memory blocks 24 to 27 in the dynamic memory 28 will be stored in the refresh counter 68.
．． It is sequentially refreshed according to the refresh address from 69. By the way, in the middle of this refresh cycle, the access request signal 16 from the processor 1117- is lowered to the 0 level, and when an access request is generated, the timing generation circuit 15 outputs the wait signal 23 to the microprocessor 11. By inputting this wait signal 23, the processor 11 enters a standby state, and the refresh being executed during this time is completed, so no problem occurs.

In this manner, in the above embodiment circuit, the dynamic memory 28 is divided into two, the memory block 24.25 with an even number address and the memory block 26.27 with an odd number address, and one memory block 24.25 or 26.27 is divided into two.
In the memory cycle in which data is accessed in the other memory block 26, 27 or 24° 25
The data is refreshed using the . Therefore, it is possible to perform refresh at the same time that data is being accessed. The operation of the microprocessor 11 is stopped and put on standby when an access request is generated after there has been no data access for a long time.
This is a very short period of time when refreshing the data, and after that, refresh can be executed at the same time as data access, so there is almost no reduction in the execution speed of the microprocessor 11 due to refreshing. Moreover, this feature becomes more and more prominent as target microprocessors become more sophisticated, for example, as they become compatible with pipeline processing. Furthermore, when data is accessed in one of the even-numbered and odd-numbered memory blocks, the other memory block only needs to be automatically refreshed, and the timing generation circuit 15 can handle both the even and odd memory blocks. Since they are commonly used and the signals generated here are simple, the circuit configuration is simpler than the conventional method, which detects idle time in the processor at high speed and inserts a refresh cycle. It can be done relatively easily.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, in the above embodiment, one word is made up of 16 bits, and both even and odd memory blocks are made up of two upper bytes and lower bytes. When the present invention is implemented in a data processing system using a microprocessor, the two memory blocks of the upper byte and the lower byte are unnecessary, and the circuit associated therewith is also unnecessary. Furthermore, in the above embodiment, the data processing device is a microprocessor, but this applies not only to access from the processor (in a data processing system using a DMA controller, it also applies to memory access from the DMA controller). Data can also be refreshed without inserting a wait cycle.

〔Effect of the invention〕

As explained above, according to the present invention, in a data processing system equipped with a dynamic memory, the execution speed of the data processing device is not reduced due to memory refresh operation, and the circuit configuration is relatively simple. A simple dynamic memory control circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention;
FIG. 2 is a timing chart thereof. DESCRIPTION OF SYMBOLS 11... Microprocessor, 15... Timing generation circuit, 24.25.26.27... Memory block, 28... Dynamic type memory, 62.63...
-Address multizolexer, 68.69...Refresh counter, 76.77...Refresh request counter. Applicant's agent Patent attorney Takehiko Suzue 21-

Claims (1)

[Claims] In a data processing system equipped with a dynamic memory, the object-ring address space of the data processing system is divided into odd and even addresses in basic word length units, and the memory is correspondingly divided into an odd number side and an even number side. A data access control means and a data refresh control means are respectively provided for the odd and even memories, and when the odd memory is in a memory cycle controlled by the data access control means, the even memory is controlled by the data access control means. The memory cycle is controlled by the refresh control means, and the even-numbered memory is controlled by the data access control means.