JP3754765B2 - Data processing device - Google Patents

Description

[0001]
(table of contents)
TECHNICAL FIELD OF THE INVENTION
Conventional technology (FIGS. 5 to 8)
Problems to be solved by the invention
Means for solving the problem (FIG. 1)
BEST MODE FOR CARRYING OUT THE INVENTION (FIGS. 2 to 4)
The invention's effect
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus having a plurality of access points (access request sources; for example, a vector processing unit and a scalar processing unit) for main memory, and in particular, improves processing when a hang-up occurs, and requests access to main memory. The present invention relates to a data processing apparatus capable of performing efficient processing.
[0003]
[Prior art]
In a general data processing apparatus, since priority is determined in advance between ports serving as access points (access request sources) for main memory, when there is an access request for a port having a high priority The port access request is always processed with priority. Therefore, when access requests for ports with high priority occur continuously, access requests for other ports with low priority will remain on the port for a long time until the access requests for ports with high priority are interrupted. It happens to be retained.
[0004]
FIG. 5 is a block diagram showing a configuration example of a general data processing apparatus. The data processing apparatus shown in FIG. 5 has a vector processing unit 11 and a scalar processing unit 12 as access request sources, and includes a priority determination circuit 3, The access processing unit 4 and the main memory 6 are included.
The vector processing unit 11 outputs an access request for the main memory 6 to the priority determination circuit 3 through the ports 21 to 24, while the scalar processing unit 12 transmits the access request to the priority determination circuit 3 through the port 25 to the main memory 6. The access request for is output. The priority order between the ports 21 to 25 is set so that the port 25 connected to the scalar processing unit 12 has priority over the ports 21 to 24 connected to the vector processing unit 11.
[0005]
Further, the main memory 6 is interleaved into 32 banks 0 to 31. The eight access buses 51 to 58 from the access processing unit 4 to the main memory 6 are formed as a set of four horizontal banks shown in FIG. In this way, the eight banks of the main memory 6 can be accessed simultaneously.
The priority determination circuit 3 includes the contents of the access requests of the ports 21 to 25, the priority between the ports 21 to 25, the contention of the access buses 51 to 58 between the ports 21 to 25, the busy status of each bank of the main memory 6 Based on the above, an access request to be processed for access (from which port an access request is to be processed) is determined.
[0006]
Here, the contention of the access buses 51 to 58 between the ports 21 to 25 is contention of the access buses 51 to 58 used by the access requests from the ports 21 to 25. A port access request with a high inter-port priority is selected by the priority determination circuit 3 and processed preferentially by the access processing unit 4. The busy status of the main memory 6 is monitored for each interleaved bank. When an access is made to a certain bank, the bank is busy only for a certain period, and it is prohibited to process other access requests for that bank. Is done.
[0007]
The access request transmitted from the vector processing unit 11 or the scalar processing unit 12 includes the following block access, single access, and random access. In addition, the access request from the vector processing unit 11 is one unit of access to one bank, and one or more units (for example, 256 units) are continuously transmitted continuously as a series of accesses.
[0008]
(1) Block access (read / write): sent from the vector processing unit 11 or the scalar processing unit 12 to the corresponding one of the ports 21 to 24 or 25, respectively, and vertically arranged in 8 columns (for example, bank) in the main memory 6 0 to 7) are simultaneously read or written. Accordingly, since the eight access buses 51 to 58 are simultaneously used in one block access, even one of the eight access buses 51 to 58 is busy or is in conflict with another bus, so that eight of them are simultaneously used. If it cannot be used, block access cannot be executed. The access request by the block access is transmitted from the vector processing unit 11 to one of the ports 21 to 24 (for example, the port 21) of the priority determination circuit 3 and from the scalar processing unit 12 to the port 25. A series of accesses from the vector processing unit 11 is simultaneously processed by the access processing unit 4 by 8 units.
[0009]
(2) Single access (read / write): Transmitted from the vector processing unit 11 or the scalar processing unit 12. Reading or writing to any one bank of the main memory 6 is performed. In one single access, only one of the eight access buses 51 to 58 is used. This access request by single access is also transmitted from the vector processing unit 11 to one of the ports 21 to 24 (for example, port 21) of the priority determination circuit 3 and from the scalar processing unit 12 to the port 25.
[0010]
(3) Random access (read / write): Transmitted only from the vector processing unit 11. Single access is simultaneously transmitted to the ports 21 to 24 of the priority determination circuit 3. In one random access, a maximum of 4 banks are simultaneously written or read, and a maximum of 4 of the 8 access buses 51 to 58 are used. This random access is an access to a series of non-consecutive main storage areas. At first, there are simultaneous access requests to the ports 21 to 24, and thereafter, access requests are successively transmitted to vacant ports. . The priority determination circuit 3 processes the access request while maintaining the order of port 21 → port 22 → port 23 → port 24 → port 21 →. That is, when there is an access request that cannot be transmitted due to competition between the ports or busy, transmission of an access request to a port located behind the access request is prohibited in order to guarantee the above-described order.
[0011]
In the data processing apparatus as described above, for example, when the access request transmitted to the port 25 with high priority is continuous single access to the same bank, the bank is always used only for the access request of the port 25. Thus, access from the other port to the bank is practically impossible until the access request of the port 25 moves to another bank or the access request is interrupted. Such a situation is called hang-up.
[0012]
Also, if a program can be written in which the condition for canceling an access request to a port with a high priority is termination of processing of an access request to a port with a low priority, the port The access request is not processed at all, and access to the port having the higher priority is processed without interruption, and as a result, access to the port having the lower priority is hung up.
[0013]
Therefore, in order to detect a hang-up and prevent the hang-up from actually occurring, a data processing apparatus as shown in FIG. 6 has also been proposed (see JP-A-6-161873). In FIG. 6, the same reference numerals as those already described indicate the same parts, and the description thereof is omitted.
The data processing device shown in FIG. 6 has a configuration in which hang-up detection circuits 71 to 75, a counter 76, and a hang-up processing circuit 9 are newly added to the data processing device shown in FIG.
[0014]
The hang-up detection circuits 71 to 75 are provided corresponding to the ports 21 to 25, respectively. When the access requests held in the ports 21 to 25 are held for a predetermined time or more, the access requests are in a hang-up state. Assuming that there is a hang-up detection signal (hang-up detection flag) 81 to 85 rising from “0” to “1”, it is output to the hang-up processing circuit 9. As will be described later with reference to FIG. 7, each of the hang-up detection circuits 71 to 75 detects hang-up while using the output of the counter 76 as a trigger signal.
[0015]
When the hang-up processing circuit 9 receives the detection signals 81 to 85 from the hang-up detection circuits 71 to 75 and one port is detected to hang up, it gives priority only to the access request of that port (priority inversion). Control), while the transmission of access requests from other ports is suppressed until this is transmitted, if two or more ports are detected to hang up, the same processing is performed for each port according to a predetermined priority order. To do. As described above, the hang-up processing circuit 9 performs priority inversion control according to the detection signals 81 to 85 from the hang-up detection circuits 71 to 75, thereby avoiding the hang-up in the priority determination circuit 3. The
[0016]
By the way, the hang-up detection circuit 71 includes an inverter 201, AND gates 202 and 204, and latch circuits 203 and 205 as shown in FIG. The other hang-up detection circuits 72 to 75 have the same configuration as the circuit 71 shown in FIG.
In FIG. 7, the output of the counter 76 is not for directly measuring the time held in the port 21, but the carry-up signal of the counter 76 is a latch circuit for a hangup prediction flag as will be described later. 203 and a trigger signal for setting a latch circuit 205 for a hang-up detection flag.
[0017]
The meaning of each signal in FIG. 7 is as follows.
(1) Port valid signal: Signal indicating that there is an access request to port 21 (to 25)
(2) Port release signal: A signal indicating that an access request held in the port 21 (to 25) is transmitted to the main memory 6 at the next timing.
(3) Trigger signal: carry-up signal of counter 76 (most significant carry signal)
Next, the operation of the hang-up detection circuit 71 (-75) shown in FIG. 7 will be described.
[0018]
First, it is assumed that the outputs of the hang-up prediction flag latch circuit 203 and the hang-up detection flag latch circuit 205 are both reset to “0”.
Now, when the trigger signal (carry-up signal) from the counter 76 becomes “1”, there is an access request to the corresponding port 21, the port valid signal becomes “1”, and it is transmitted at the next timing. If the port release signal is not “0”, the port release signal is inverted to “1” by the inverter 201 and all three inputs (trigger signal, port valid signal, port release signal) of the AND gate 202 are “ As a result, the output of the hang-up prediction flag latch circuit 203 is set to “1”.
[0019]
If an access request is issued until the trigger signal from the counter 76 next becomes “1” (the time count Nτ of the counter 76 is set) (that is, if the port release signal becomes “1”), it hangs. The up prediction flag latch circuit 203 is reset. If the trigger signal becomes “1” without resetting the hang-up prediction flag latch circuit 203, the two inputs (the output of the latch circuit 203 and the trigger signal) of the AND gate 204 become “1”. The output of the hang-up detection flag latch circuit 205 is set to “1”.
[0020]
Thereafter, when the access request held in the port 21 is transmitted to the main memory 6 by the function of the hang-up processing circuit 9 (that is, when the port release signal becomes “1”), the hang-up prediction flag latch circuit The outputs of 203 and the hang-up detection flag latch circuit 205 are both reset to "0".
With such a hang-up detection circuit 71 (-75), a hang-up may be detected if the time during which an access request is held in the port 21 exceeds Nτ. Is done. In the hang-up detection circuit 71 (-75), the detection of hang-up does not occur continuously in a short time, but occurs at the minimum Nτ interval, so the hang-up process occupying the entire access process is relatively low. Can be suppressed.
[0021]
8A to 8F are specific time charts when the hangup is detected by the hangup detection circuit 71 (to 75). In the example shown in FIGS. 8A to 8F, the time count N of the counter 76 is 256. As shown in FIGS. 8A and 8B, the counter 76 starts counting from “0”. The trigger signal rises to “1” at the timing of counting “255”.
[0022]
As shown in FIGS. 8B to 8F, the hangup prediction flag is set at the rising timing of the first trigger signal after the access request is held in the port 21 (after the port valid signal becomes “1”). The output (hangup prediction flag) of the latch circuit 203 is set to “1”.
If the same access request is still held in the port 21 at the rise time of the next trigger signal after 256τ, the output of the hang-up detection flag latch circuit 205 (hang-up detection flag) at the rise timing of the trigger signal. ) Is set to “1”, and a hang-up is detected (the hang-up detection signal 81 rises from “0” to “1”).
[0023]
That is, when the time during which the access request is held in the port 21 exceeds 256τ, the hang-up is detected before the holding time reaches 512τ. The outputs of the hangup prediction flag latch circuit 203 and the hangup detection flag latch circuit 205 are both reset to “0” when the port release signal for the access request becomes “1”.
[0024]
As described above, in the above-described data processing apparatus, means for detecting that the time during which the access request is held in each of the ports 21 to 25 exceeds a predetermined time T (for example, Nτ or 256τ) (hangup detection) A circuit that is set to “1” when the means detects that the holding time of the access request exceeds the time T, and becomes “0” when the access request is transmitted to the main memory 6. The hang-up process is controlled using (hang-up detection signals 81 to 85).
[0025]
[Problems to be solved by the invention]
By the way, in the data processing apparatus configured as described above and performing hangup detection / hangup processing, for example, while I / O access is access with distance and the same bank is being accessed with a long length, a vector Consider the case where there is an access request with the maximum length of store access.
[0026]
If there is no access contention, the vector instruction can use all the 8 columns in 1 column, so it ends with 2048/8 = 256τ. However, the access with the distance of the long length as described above is preferential. If it is executed and conflicts with its access, it is executed only once when a hangup is detected for the port holding the vector instruction. Therefore, if the value of the access request holding counter is 512 (maximum time taken to detect hang-up; in the example shown in FIG. 8, the counter 76 counts 256 cycles × 2), the vector instruction is processed (2048). / 8) * 512 = 131072τ, and there is a problem in that the processing performance of the data processing apparatus is significantly reduced.
[0027]
The present invention has been devised in view of such a problem, and provides a data processing apparatus that can efficiently process an access request in which a hang-up state continues for a long time and has improved processing performance. The purpose is to do.
[0028]
[Means for Solving the Problems]
FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the data processing apparatus of the present invention includes a plurality of access request sources 1, a main memory 6 interleaved in a plurality of banks, and an access request source 1. A plurality of ports 2 that accept access requests to the main memory 6, a priority determination circuit 3 that determines the priority of access requests held in these ports 2, and a plurality of ports according to the priority determined by the priority determination circuit 3. And an access processing unit 4 for transmitting an access request held in the port 2 to the main memory 6, and a hang-up detection circuit 7, a hang-up processing circuit 9, and a reference time setting unit 10. Yes.
[0029]
Here, the hang-up detection circuit 7 is provided corresponding to each of the plurality of ports 2 and detects the access request as a hang-up when the corresponding port 2 holds an access request for a reference time or more. The hang-up processing circuit 9 performs hang-up processing using the detection result of the hang-up detection circuit 7 as an element for determining the priority order of access requests. When the access request is continuously held in the port 2 even after the hang-up processing by the hang-up processing circuit 9 is performed in accordance with the hang-up detection by 7, the reference time is set to be shortened. 1).
[0030]
In the data processing apparatus of the present invention configured as described above, the same access request is continuously sent to the port 2 even after the hangup processing by the hangup processing circuit 9 is performed in accordance with the hangup detection by the hangup detection circuit 7. If it is kept, the reference time setting unit 10 sets the reference time, which is a hang-up detection reference by the hang-up detection circuit 7, to a shorter time. Accordingly, the interval of hangup detection by the hangup detection circuit 7 is shortened, and it becomes possible to efficiently process an access request in which the hangup state continues for a long time.
[0031]
The hang-up processing circuit 9 is configured to perform inversion control of the priority order of access requests according to the hang-up detection by the hang-up detection circuit 7 as the hang-up process, and the reference time setting unit 10 is A priority inversion counter that counts the number of times the priority inversion control is performed by the hang-up processing circuit 9, and a reference time switching that switches the reference time to a shorter reference time according to the count value of the priority inversion counter (Claim 2). At this time, the priority order inversion counter is reset in response to valid-off of the port 2 holding the access request.
[0032]
That is, as the number of times of priority inversion control by the hang-up processing circuit 9 is increased, it can be determined that the same access request is continuously held in the port 2. According to the count value, the reference time switching circuit switches the reference time as a hang-up detection reference by the hang-up detection circuit 7 to a shorter time, thereby making it possible to access the hang-up state for a long time as described above. Requests can be processed efficiently.
[0033]
The hang-up detection circuit 7 provided corresponding to each of the plurality of ports 2 may be configured to detect hang-up using the count output of a common counter. . In this case, hang-up detection can be performed without providing a hang-up detection counter (a counter used for measuring the port holding period of the access request) for each of the plurality of ports 2.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2 is a block diagram showing a configuration of a data processing apparatus as an embodiment of the present invention. In FIG. 2, the five ports 21 to 25, the eight access buses 51 to 58, the five hangup detection circuits 71 to 75, and the five hangup detection signals 81 to 85 shown in FIG. 5 and FIG. Are unified into one code, that is, unified as port 2, access bus 5, hang-up detection circuit 7 and hang-up detection signal 8. In FIG. 2, the same reference numerals as those already described indicate the same parts, and detailed description thereof will be omitted.
[0035]
As shown in FIG. 2, the data processing apparatus according to the present embodiment has a vector processing unit 11 and a scalar processing unit 12 as access request sources, as well as the apparatus shown in FIG. In addition to the unit 4, the main memory 6, and the hangup processing circuit 9, the hangup detection circuit 7 for each port 2 is configured. In this embodiment, the hangup detection circuit 7 for each port 2 includes A reference time setting unit 10 is newly added.
[0036]
Here, the vector processing unit 11 outputs an access request to the main memory 6 to the priority determination circuit 3 via the four ports 2, while the scalar processing unit 12 outputs the priority determination circuit 3 via one port 2. In addition, an access request for the main memory 6 is output.
The main memory 6 is interleaved into 32 banks 0 to 31. The access processing unit 4 extends eight access buses 5 from the access processing unit 4 to the main memory 6 as a set of four banks in the horizontal direction shown in FIG. As a result, the eight banks of the main memory 6 can be accessed simultaneously.
[0037]
The priority determination circuit 3 should perform access processing based on the contents of the access request of each port 2, the priority between the ports 2, the contention of the access bus 5 between the ports 2, the busy status of each bank of the main memory 6 and so on. The access request (from which port the access request should be processed; the priority of the access request) is determined.
The hang-up detection circuit 7 is provided for each port 2 and is configured in the same way as described with reference to FIG. 7 with reference to FIG. A hang-up detection signal (hang-up detection flag) 8 that rises from “0” to “1” is output to the hang-up processing circuit 9 assuming that the access request is in a hang-up state when held for a reference time or longer. It is.
[0038]
As will be described later with reference to FIG. 3, each hang-up detection circuit 7 of the present embodiment also outputs the count output of the common counter 76 to the latch circuit 203 for the hang-up prediction flag and the latch for the hang-up detection flag. The hang-up is detected while being used as a trigger signal for setting the circuit 205.
The hang-up processing circuit 9 uses a detection result of each hang-up detection circuit 7 as a determination factor for the priority order of access requests (priority of access requests according to hang-up detection by the hang-up detection circuit 7). Order inversion control).
[0039]
Then, the reference time setting unit 10 continuously holds the same access request in the port 2 even after the hang-up processing by the hang-up processing circuit 9 is performed along with the hang-up detection by each hang-up detection circuit 7. In this case, the reference time in the hang-up detection circuit 7 attached to the port 2 is forcibly shortened.
[0040]
The reference time setting unit 10 includes a priority order inversion counter 101, a switching signal generation circuit 102, a selector 103, an AND gate 104, and inverters 105 and 106, as shown in FIG. 3 also shows the detailed configuration of the hang-up detection circuit 7 in the present embodiment, the detailed configuration of the hang-up detection circuit 7 is the hang-up detection circuit 71 (˜75) shown in FIG. ), The description is omitted.
[0041]
Here, the priority inversion counter 101 is for counting the number of times the priority inversion control is performed by the hang-up processing circuit 9. In the present embodiment, based on the input / output of the hang-up detection flag latch circuit 205 in the hang-up detection circuit 7, the timing for performing priority inversion control in accordance with the hang-up detection is detected. Counting up.
[0042]
That is, when the output of the latch circuit 205 (hangup detection signal 8) is “0”, the timing when the set input to the latch circuit 205 (output of the AND gate 204) becomes “1” (that is, the hangup detection signal 8 is Since the timing of switching from “0” to “1” is the priority inversion control timing, the inverter 105 that inverts the output of the latch circuit 205, the output of the inverter 105, and the set input to the latch circuit 205 By using the AND gate 104 that outputs the logical product of the above, the inversion timing can be detected as the rise of the output of the AND gate 104. Then, by using the output of the AND gate 104 as a count-up signal of the counter 101, the counter 101 counts the number of times that the hang-up processing circuit 9 performs priority inversion control.
[0043]
Note that a signal obtained by inverting the port valid signal of the port 2 to be hang-up detected by the inverter 106 is input to the priority inversion counter 101 of this embodiment as a reset signal. Accordingly, the counter 101 is configured to be reset in response to valid-off of the port 2 to be detected for hang-up (completion of access request processing).
[0044]
The switching signal generation circuit 102 generates a switching signal according to the count value by the priority inversion number counter 101 and gives it to the selector 103.
Then, the selector (reference time switching circuit) 103 responds to the switching signal from the switching signal generating circuit 102 and outputs bit lines 76-1 to 76-n (counter outputs of the n-bit counter) which are count outputs of the counter 76. 1) is selected and switched to the AND gates 202 and 204 of the hang-up detection circuit 7 as a trigger signal for the latch circuits 203 and 305.
[0045]
That is, in the selector 103 of this embodiment, the reference time in the hang-up detection circuit 7 is switched to a shorter reference time as the count value of the priority inversion number counter 101 increases. For example, the selector 103 is switched so that the reference time becomes 256τ, 64τ, 16τ, 4τ, 4τ,... Corresponding to 0, 1, 2, 3, 4,. Control [selection / switching control of trigger signal (carry-up signal from bit lines 76-1 to 76-n of counter 76)] is performed. More specific and detailed operations will be described later with reference to FIGS.
[0046]
The meaning of each signal in FIG. 3 is as follows.
(1) Port valid signal: A signal indicating that there is an access request to port 2 of the hang-up detection target.
(2) Port release signal: A signal indicating that the access request held in the port 2 to be detected for hangup is transmitted to the main memory 6 at the next timing.
(3) Trigger signal: Carry-up signal selected by the selector 103 from the bit lines 76-1 to 76-n of the counter 76
Next, operations of the hang-up detection circuit 7 and the reference time setting unit 10 shown in FIG. 3 will be described with reference to FIGS.
[0047]
4A to 4I are specific time charts for explaining the hang-up detection operation by the hang-up detection circuit 7 and the reference time switching operation by the reference time setting unit 10 according to the present embodiment. . However, since the operation of the hang-up detection circuit 7 has been described above with reference to FIGS. 7 and 8 as the operation of the hang-up detection circuit 71, a detailed description thereof will be omitted.
[0048]
First, the outputs of the hang-up prediction flag latch circuit 203 and the hang-up detection flag latch circuit 205 are both reset to “0”, and the count value by the priority inversion counter 101 is also reset to “0”. To do.
When the count value of the priority inversion counter 101 is “0”, the counter 76 starts counting from “0” and counts “255” [count value 256 (= 2 ⁸ )] Is assumed to be selected as a trigger signal by the selector 103 and input to the AND gates 202 and 204.
[0049]
As shown in FIGS. 4A to 4F, also in the present embodiment, after the access request is held in the port 2 that is the hang-up detection target at the timing t0 (after the port valid signal becomes “1”). At the rising timing (256 count timing) t1 of the first trigger signal, the output (hangup prediction flag) of the hangup prediction flag latch circuit 203 is set to “1”.
[0050]
If the same access request is still held at port 2 at the rise time t2 of the next trigger signal after 256τ, the output (hangup) of the hangup detection flag latch circuit 205 at the rise timing t2 of the trigger signal. Detection flag) is set to “1”, and a hangup is detected (hangup detection signal 8 rises from “0” to “1”). That is, if the time during which the access request is held in the port 2 exceeds 256τ, a hang-up is detected before the holding time reaches 512τ.
[0051]
When a hangup is detected in this way, as described with reference to FIG. 8, the hangup processing circuit 9 performs priority inversion control, the access request is processed, and the port release signal for the access request is received. At timing t3 when the timing becomes “1”, the outputs of the hang-up prediction flag latch circuit 203 and the hang-up detection flag latch circuit 205 are both reset to “0”.
[0052]
On the other hand, in the reference time setting unit 10 in this embodiment, as described above with reference to FIG. 3, the output of the AND gate 104 also rises to “1” at the timing t2 when the hang-up detection signal 8 rises from “0” to “1”. As shown in FIG. 4G, the count value by the priority inversion counter 101 is changed from “0” to “1”.
The count value “1” of the counter 101 is set to “0” when the port 2 is released and the port valid signal becomes “0” in accordance with the priority inversion control by the hangup processing circuit 9 according to the hangup detection. In this case, after the port release signal rises at the timing t3 as shown in FIG. 4D, an access request is sent to the port 2 to be detected for hangup as shown in FIG. 4C. It is assumed that the port valid signal remains “1”.
[0053]
In such a case, in the reference time setting unit 10 of the present embodiment, as shown in FIG. 4 (h), the switching signal generation circuit 102 according to the count value by the priority inversion counter 101 becoming “1”. A switching signal is output from the selector 103 to the selector 103. When the count value of the counter 101 is “1” by this switching signal, the counter 76 starts counting from “0” and counts “63” [count value 64 (= 2 ⁶ )] Is selected as a trigger signal, and is input from the selector 103 to the AND gates 202 and 204.
[0054]
Therefore, as shown in FIGS. 4A to 4F, when the count value of the priority inversion number counter 101 becomes “1”, the hang-up prediction flag latch circuit 203 has the count value t4 of the counter 76 at 64 count timing t4. The output (hangup prediction flag) is set to “1”.
Further, if the same access request is still held in the port 2 at the trigger signal rise time t5 after 64τ, the output of the hangup detection flag latch circuit 205 (hangup detection flag) at the trigger signal rise timing t5. Is set to “1” and hang-up is detected (hang-up detection signal 8 rises from “0” to “1”). In other words, when the count value of the priority inversion counter 101 is “1”, if the time that the access request is held in the port 2 exceeds 64τ, the hangup is detected again until the holding time reaches 128τ. Will be.
[0055]
When a hangup is detected in this way, the hangup processing circuit 9 also performs priority inversion control, processes the access request, and sets the port release signal for the access request to “1”. At t6, the outputs of the hang-up prediction flag latch circuit 203 and the hang-up detection flag latch circuit 205 are both reset to “0”.
[0056]
Further, at the timing t5 when the hang-up detection signal 8 rises from “0” to “1”, the output of the AND gate 104 also rises to “1”, and the count value by the priority inversion number counter 101 as shown in FIG. Becomes “2” from “1”. Accordingly, as shown in FIG. 4I, a switching signal is output from the switching signal generating circuit 102 to the selector 103, and when the count value of the counter 101 is “2”, the counter 76 is changed from “0”. Timing for starting counting and counting “15” [count value 16 (= 2 ^Four )] Is selected as a trigger signal, and is input from the selector 103 to the AND gates 202 and 204.
[0057]
In the example shown in FIGS. 4A to 4I, the port 2 is released by the priority inversion control accompanying the hang-up detection at the timing t5, and the port valid signal becomes “0” at the timing t7. . Accordingly, the count value of the priority inversion counter 101 is reset to “0”, the switching signal generation circuit 102 and the selector 103 are also reset, and the reference time setting unit 10 is in the initial state (hang-up detection circuit 7 In addition, the process returns to the state in which the carry-up signal that rises at the 256 count timing among the signals from the counter 76 is selectively input as a trigger signal.
[0058]
If the same access request continues to be held in the port 2 after the timing t7, the count value by the priority inversion number counter 101 increases to “2”, “3”, “4”,. Accordingly, as described above, the carry-up signal rising at the count timing of 16, 4, 4,... Out of the signals from the counter 76 is selected as the trigger signal by the switching signal generation circuit 102 and the selector 103, and the hang-up detection circuit. 7 is input.
[0059]
As described above, in the data processing device of this embodiment, it can be determined that the same access request is continuously held in the port 2 as the number of times of priority inversion control by the hang-up processing circuit 9 increases. From the signal from the counter 76, a signal that rises at a shorter interval is selected by the switching signal generation circuit 102 and the selector 103 according to the count value by the priority inversion number counter 101, and the hang-up detection circuit 7 (AND The gates 202 and 204) are inputted as trigger signals.
[0060]
As a result, the reference time used as the hang-up detection reference by the hang-up detection circuit 7 is switched to a shorter time, the hang-up detection interval by the hang-up detection circuit 7 is shortened, and the hang-up state continues for a long time. The access request to be processed can be processed efficiently, and the data processing performance is greatly improved.
For example, when an access request is made with the maximum length of vector store access while the I / O access is an access with a distance and the same bank is being accessed with a long length, as described above, the vector instruction Ends with 2048/8 = 256τ if there is no access contention, but it takes (2048/8) * 512 = 131072τ if there is access contention.
[0061]
However, according to the data processing apparatus of the present embodiment, the reference time is 256τ, 64τ, 16τ, 4τ, 4τ, corresponding to the count values 0, 1, 2, 3, 4,. ... (the maximum time required for hang-up detection is 512τ, 128τ, 32τ, 8τ, 8τ,...), And the switching time of 131072τ is set to 2696τ by controlling the switching of the selector 103. Therefore, the processing speed can be increased by about 50 times.
[0062]
In the data processing apparatus of this embodiment, the hang-up detection circuit 7 provided for each port 2 detects hang-up using the count output of the common counter 76. There is no need to provide a counter for measuring each port 2 and the hardware can be reduced. Even if the port 2 is increased, the increase in the counter does not cause an increase in hardware.
[0063]
In the above-described embodiment, the reference time in the hang-up detection circuit 7 is switched according to the count value of the priority inversion number counter 101. However, the type of access request source (vector processing unit 11, scalar processing) The reference time in the hang-up detection circuit 7 may be set to be shortened according to the unit 12).
In the above-described embodiment, the reference time is shortened by selecting a signal that rises at a shorter interval from the signals from the counter 76, but the time measured by a timer or the like is subtracted and set. You may comprise so that the shortening of reference time may be performed using a method.
[0064]
Further, in the above-described embodiment, the number of ports 2 is set to 5, and a specific numerical value is shown as a reference time set according to the count value of the priority inversion number counter 101. It is not limited to these numerical values.
[0065]
【The invention's effect】
As described above in detail, according to the data processing apparatus of the present invention, when the same access request is continuously held in the port even after the hang-up process is performed in accordance with the hang-up detection, the hang-up is performed. Since the up detection interval (reference time) is shortened, an access request in which the hang-up state continues for a long time can be efficiently processed, and the data processing performance is greatly improved. ).
[0066]
In addition, the hang-up detection circuit corresponding to each of the plurality of ports is configured to detect the hang-up using the count output of the common counter, and is used to measure the port holding period of the access request. There is no need to provide a counter for each port, hardware can be reduced, and even if the number of ports is increased, the increase in hardware due to an increase in counters is not caused (claim 4).
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a block diagram showing a configuration of a data processing apparatus as an embodiment of the present invention.
FIG. 3 is a block diagram showing a detailed configuration of a hang-up detection circuit and a reference time setting unit in the data processing apparatus of the present embodiment.
FIGS. 4A to 4I are time charts for explaining operations of a hang-up detection circuit and a reference time setting unit in the present embodiment.
FIG. 5 is a block diagram illustrating a configuration example of a general data processing apparatus.
FIG. 6 is a block diagram illustrating a configuration example of a conventional data processing apparatus that performs hang-up detection.
FIG. 7 is a block diagram illustrating a configuration example of a hang-up detection circuit.
8A to 8F are time charts for explaining the operation of the hang-up detection circuit shown in FIG.
[Explanation of symbols]
1 Access request source
11 Vector processing unit (access request source)
12 Scalar processing part (access request source)
2, 21-25 ports
3 Priority decision circuit
4 Access processing section
5,51-58 Access bus
6 Main memory
7,71-75 Hangup detection circuit
76 counter
76-1 to 76-n bit lines
8, 81-85 Hangup detection signal (hangup detection flag)
9 Hang-up processing circuit
10 Reference time setting section
101 Priority inversion counter
102 Switching signal generation circuit
103 selector (reference time switching circuit)
104 AND gate
105,106 inverter
201 inverter
202,204 AND gate
203 Latch circuit for hangup prediction flag
205 Hang-up detection flag latch circuit

Claims (4)

Multiple access request sources;
Main memory interleaved in multiple banks,
A plurality of ports for receiving access requests to the main memory from the access request source;
A priority determination circuit for determining the priority order of access requests held in the plurality of ports;
An access processing unit for transmitting an access request held in the plurality of ports to the main memory according to the priority order determined by the priority determination circuit;
A hang-up detection circuit that is provided corresponding to each of the plurality of ports and detects the access request as a hang-up when an access request is held in the corresponding port for a reference time or more;
In a data processing apparatus comprising a hang-up processing circuit for performing a hang-up process using the detection result by the hang-up detection circuit as a determination factor for the priority order of access requests,
When the access request is continuously held in the port even after the hangup processing by the hangup processing circuit is performed in accordance with the hangup detection by the hangup detection circuit, the reference time for setting the reference time to be shortened A data processing apparatus comprising a setting unit. The hang-up processing circuit is configured to perform inversion control of the priority order of access requests according to hang-up detection by the hang-up detection circuit as the hang-up processing,
The reference time setting unit counts the number of times the priority inversion control is performed by the hang-up processing circuit, and the reference time is shortened according to the count value by the priority inversion number counter. 2. A data processing apparatus according to claim 1, comprising a reference time switching circuit for switching to a reference time. 3. The data processing apparatus according to claim 2, wherein the priority inversion counter is reset in response to valid-off of the port holding the access request. 4. The hang-up detection circuit provided corresponding to each of the plurality of ports detects the hang-up using a count output of a common counter. A data processing apparatus according to any one of the above.

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