JP5314516B2 - Storage device and packet relay device - Google Patents

Description

  The present invention relates to a storage device and a packet relay device.

  Conventionally, due to an increase in the amount of data handled by a computer, the speed of operations such as write processing and read processing on a memory has been increased. In particular, a packet relay apparatus that relays data on a network is required to perform an accurate operation on a memory at a high speed with a rapid increase in data transfer amount in recent years.

  The packet relay device is a device that transfers data to a transmission destination based on transmission destination information included in the packet at the time of data transfer, and temporarily stores received data until the data is transferred to the transmission destination. Save to. Then, the packet relay device sequentially reads data from the memory and transfers the read data to the transmission destination corresponding to the transmission destination information.

  Here, when data is read from the memory, a read error due to a component failure or a soft error may occur. Therefore, various techniques are known in recent years for dealing with read errors that have occurred.

  For example, as a technique for correcting a data read error, there is a technique using an ECC (Error Correcting Code) circuit. As shown in FIG. 7, the packet relay apparatus having the ECC circuit adds ECC to the input data and writes the data with the ECC added to the memory. Then, the packet relay apparatus checks an error in the data read from the memory, and when an error is detected, corrects the detected error and outputs the corrected data. FIG. 7 is a diagram for explaining error correction using an ECC circuit.

  However, in the technique of correcting an error using the above-described ECC circuit, a 1-bit error can be corrected, but an error of 2 bits or more cannot be corrected. Accordingly, in a packet relay apparatus that manages packets by segmenting them, when an error of 2 bits or more occurs and the situation cannot be corrected, the assembly order of the packets after the occurrence of the error is not known, and the continuous operation becomes impossible.

  Therefore, as a storage device that can handle even when an error of 2 bits or more occurs, a storage device that stores data in duplicate by duplicating the memory is known (for example, see Patent Document 1). ). Specifically, as shown in FIG. 8, in the storage device that stores data twice, the memory has two storage areas of 0 and 1 planes, and the same data is stored on each of the 0 and 1 planes. Write. When reading data from the two storage areas by the read control unit, the storage device first selects one of the areas by the selector, reads the data from the selected area, and passes through the FF (flip flop). Perform error checking. If no error is detected, the read control unit outputs the data held in the FF.

  On the other hand, when an error is detected, the read control unit reads data from the other area again, executes the above-described processing, and then outputs the data. FIG. 8 is a diagram for explaining memory duplication.

Japanese Laid-Open Patent Publication No. 2-048755

  By the way, with the above-described technique for storing data twice, when an error is detected, it is necessary to perform a process of reading data again, so that high-speed operation becomes difficult. Specifically, the read control unit sequentially inputs read addresses to the memory in accordance with a rising cycle of a CLK (Clock) signal that is a signal for synchronizing processing. For example, as shown in FIG. 9, the read control unit inputs a 0-plane address 1 that is a read address for reading data from the 0-plane in accordance with the rising edge of CLK1. Further, as shown in FIG. 9, the read control unit sequentially inputs the 0-plane address 2 to the 1-plane address 2 to the memory in synchronization with the rise of CLK2 and 3 and the like.

  Then, data corresponding to the input read address is output from the memory in synchronization with the rising edge of CLK next to the CLK to which the read address is input. For example, as shown in FIG. 9, the 0 plane data1 corresponding to the 0 plane address 1 is output from the 0 plane of the memory in synchronization with the rise of CLK2. Further, as shown in FIG. 9, the 0 plane data 2 to 1 plane data 2 corresponding to the 0 plane address 2 to 1 plane address 2 are sequentially output from the memory at the rising edge of CLK3, 4 and the like.

  After that, the read control unit checks the parity error of the data in synchronization with the rising edge of the next CLK after the data is output. For example, as shown in FIG. 9, the read control unit checks the parity error of the 0 plane data1 at the rising edge of CLK3. Further, as shown in FIG. 9, the read control unit sequentially checks the parity error of each data in accordance with the rising edge of CLK4 or 5.

  That is, it takes a period of two CLK cycles until the read control unit reads data from the memory and the parity error check of the read data is completed. FIG. 9 is a time chart for explaining data reading from the duplicated memory, and PTY shown in the drawing indicates parity.

  Here, when an error is detected in the parity error check, the read control unit assigns a read address to the other storage area in synchronization with the rising edge of the next CLK after the parity error check. input. For example, when an error is detected in the 0 plane data 2 corresponding to the 0 plane address 2, the read control unit reads the data stored in the 1 plane at the rising edge of CLK 5 as shown in FIG. 1 side address 2 which is a read address of. As described above, data output and parity error check are executed in accordance with the rising period of CLK.

  Therefore, after a parity error is detected in the data read from one storage area, it takes time for three CLK cycles until the data is read from the other storage area and the parity error check of the read data is completed. .

  That is, the above-described conventional technique has a problem that accurate read processing cannot be performed at high speed. In addition, if the storage device is not only a packet relay device but also a device that is required to perform an accurate operation at a high speed, as described above, the same problem that an accurate read process cannot be performed at a high speed. was there.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object thereof is to provide a storage device and a packet relay device capable of performing accurate read processing at high speed. .

  In order to solve the above-described problems and achieve the object, in this apparatus, the storage unit stores data in each of the first area and the second area. The data read processing unit reads out the data stored in the first area in synchronization with the rising cycle of the first clock signal, and the rising interval is the same as that of the first clock signal. The data stored in the second area is read in synchronization with the rising cycle of the clock signal. The detection unit detects the presence / absence of a parity error in each of the data read by the data read processing unit, and the data output unit detects the data in which no parity error is detected based on the detection result by the detection unit. Is output to a predetermined output unit.

  The disclosed apparatus can perform accurate reading processing at high speed.

FIG. 1A is a schematic diagram illustrating an overview of the packet relay apparatus according to the first embodiment. FIG. 1-2 is a diagram for explaining the characteristics of the packet relay device according to the first embodiment. FIG. 2 is a block diagram for explaining the configuration of the packet relay apparatus according to the first embodiment. FIG. 3 is a diagram for explaining the selector control unit. FIG. 4 is a diagram for explaining the procedure of the writing process by the packet relay device according to the first embodiment. FIG. 5 is a diagram for explaining the procedure of the reading process performed by the packet relay apparatus according to the first embodiment. FIG. 6 is a diagram for explaining the pointer address. FIG. 7 is a diagram for explaining error correction using the ECC circuit. FIG. 8 is a diagram for explaining memory duplication. FIG. 9 is a time chart for explaining data reading from the duplicated memory.

  Exemplary embodiments of a storage device and a packet relay device disclosed in the present application will be described below in detail with reference to the accompanying drawings. In the following, a packet relay device incorporating a storage device disclosed in the present application will be described as an example.

[Outline and Features of Packet Relay Device in Embodiment 1]
First, the outline and features of the packet relay apparatus according to the first embodiment will be described with reference to FIGS. 1-1 and 1-2. 1-1 is a diagram for explaining an outline of the packet relay device according to the first embodiment, and FIG. 1-2 is a diagram for explaining features of the packet relay device according to the first embodiment.

  The packet relay apparatus according to the first embodiment is an apparatus that transfers data to a transmission destination based on transmission destination information included in packet data (hereinafter referred to as data), and is synchronized with a CLK (Clock) signal. The outline is to execute various processes in the transfer.

  Specifically, as illustrated in FIG. 1-1A, the packet relay apparatus according to the first embodiment includes a packet processing unit that executes various processes in data transfer at the rising edge of CLK. As shown in FIG. 1-1A, the packet processing unit writes “input processing data” to the memory at the rising edge of CLK, and writes it to the memory at the rising edge of CLK. A “read processing unit” that reads and outputs the read data.

  Here, as shown in FIG. 1-1A, the packet relay apparatus according to the first embodiment incorporates a memory having two storage areas of the 0-plane and the 1-plane. For example, the packet relay apparatus according to the first embodiment incorporates a DDR (Double Data Rate) memory.

  The write processing unit writes the input data to the 0th and 1st planes at the rising edge of CLK.

  Further, the read processing unit reads data from the 0th and 1st planes at the rising edge of CLK, respectively.

  Then, the read processing unit checks the parity error of the data read from each of the 0th and 1st planes at the rising edge of CLK, and outputs data for which no parity error has been detected.

  The packet processing unit performs write processing, read processing, and parity error detection in synchronization with CLK (CLK1, CLK2, CLK3, CLK4, and CLK5) rising at the same time interval, as shown in FIG. Execute processing and output processing.

  Here, the packet relay apparatus according to the first embodiment is mainly characterized in that accurate read processing can be performed at high speed. Briefly explaining this main feature, the packet relay apparatus according to the first embodiment uses the normal CLK (normal CLK) and the inverted CLK obtained by inverting the normal CLK, as shown in FIG. Various processes in data transfer are executed. That is, the packet relay apparatus according to the first embodiment executes processing in synchronization with the falling edge of the normal CLK by matching the rising edge of the inverted CLK.

  First, the write processing unit generates inverted data obtained by inverting a bit string of input data (hereinafter referred to as normal data). For example, as illustrated in FIG. 1A, when the normal data “bit string: 11010” is input, the write processing unit generates inverted data “bit string: 00101”.

  Then, the write processing unit writes normal data on the 0 side in accordance with the rising edge of the normal CLK, and writes the inverted data on the 1 side in accordance with the rising edge of the inverted CLK. The same address is assigned to the 0th and 1st surfaces. For example, the write processing unit writes the first “1” of the normal data “bit string: 11010” to the 0th surface of the memory in synchronization with the rising edge of the normal CLK1 shown in FIG. Then, the write processing unit writes the first “0” of the inverted data “bit string: 00101” to one surface of the memory in synchronization with the rising edge of the inverted CLK1. In other words, the write processing unit writes two data on the 0th and 1st surfaces in a time corresponding to one CLK cycle.

  Similarly, the write processing unit sequentially writes the remaining normal data “1010” on the 0 plane in accordance with the rising edges of the normal CLK 2 to 5, and sequentially sets the remaining inverted data “0101” to 1 in accordance with the rising edges of the inverted CLK 2 to 5. Write on the surface. As a result, as shown in FIG. 1-2A, the write processing unit stores the bit string “101001001” of the synthesized data obtained by synthesizing the normal data and the inverted data in two storage areas to which the same address is assigned. Write separately.

  The read processing unit reads the composite data stored separately in the two storage areas to which the same address is assigned. Specifically, the read processing unit reads the normal data from the 0th surface of the memory at the rising edge of the normal CLK, and reads the inverted data from the 1st surface of the memory at the rising edge of the inverted CLK.

  For example, when the read processing unit reads the composite data “bit string: 101001001” stored separately on the 0th and 1st surfaces of the memory to which the same address is assigned, the read processing unit is illustrated in FIG. As described above, the normal data of the composite data is sequentially read from the 0 plane in synchronization with the rising edges of the normal CLK1 to CLK5. Further, as illustrated in FIG. 1-2B, the read processing unit sequentially reads the inverted data of the composite data from one surface in accordance with the rise of the inversion CLK1 to CLK5.

  Then, the read processing unit performs a parity error check using a parity bit previously assigned to the read data. For example, as shown in FIG. 1-2B, the read processing unit sequentially checks the parity error of the 0-plane read data read from the 0-plane of the memory in accordance with the rising edge of the normal CLK 2-6.

  The read processing unit checks the parity error for the data read from one surface of the memory after inverting the bit string. For example, the packet processing unit, as shown in FIG. 1-2B, shows a parity error of “bit string: 11010” obtained by inverting one-side read data “bit string: 00101” read from one face of the memory. Is checked at the rising edge of inversion CLK2-6.

  Then, the packet processing unit compares the 0-plane read data and the 1-plane read data, and outputs data in which the bit in which the error has occurred is switched to a normal bit to a predetermined output unit. For example, as shown in FIG. 1-2B, a parity error is caused by the fact that the fourth bit of the 0-plane read data is changed from “1” to “0” in the parity error check of normal CLK5. Is detected. Further, as shown in FIG. 1-2B, it is assumed that no parity error is detected in the parity error check of the inverted CLK5.

  In the above case, as shown in FIG. 1-2 (B), the packet processing unit normally sets the fourth “0” of the 0-plane read data “bit string: 11000” in synchronization with the rising edge of CLK6. The read data “bit string: 11010” is switched to the fourth “1”. Then, the packet processing unit outputs the output data “bit string: 11010” obtained by switching the bit in which the error has occurred to a normal bit to a predetermined output unit.

  Note that the packet processing unit includes “0-side read data: normal, 1-side read data: normal”, “0-side read data: normal, 1-side read data: error” and “0-side read data: error, 1-side read”. In the case of “data: error”, the 0-plane read data is output to a predetermined output unit. Further, as described above, the packet processing unit outputs the one-side read data to the predetermined output unit when “0-side read data: error, one-side read data: normal”.

  The packet processing unit executes data switching after the parity error check in accordance with the rising edge of the normal CLK.

  For this reason, the packet relay apparatus according to the first embodiment can switch a bit in which an error is detected to a normal bit in a time corresponding to one CLK cycle, and performs an accurate read process as described above. It can be performed at high speed.

[Configuration of Packet Relay Device in First Embodiment]
Next, the configuration of the packet relay apparatus according to the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram for explaining the configuration of the packet relay apparatus according to the first embodiment.

  As illustrated in FIG. 2, the packet relay device 10 according to the first embodiment includes a memory 20, a packet processing unit 30, an input I / F 40, and an output I / F 41.

  The input I / F 40 outputs packet data (hereinafter referred to as data) input via a network (not shown) to the packet processing unit 30.

  The output I / F 41 outputs the data output from the packet processing unit 30 to a transmission destination connected via a network (not shown).

  The memory 20 stores the data input via the input I / F 40, and particularly as closely related to the present embodiment, as shown in FIG. It has two storage areas. Here, the same address is assigned to the 0th and 1st surfaces.

  The 0 plane 21 stores a bit string of data input through the input I / F 40 (hereinafter referred to as normal data).

  The first surface 22 stores inverted data obtained by inverting normal data by a packet processing unit 30 described later.

  The packet processing unit 30 executes various processes in data transfer, and particularly includes a write processing unit 50 and a read processing unit 60 that are closely related to the present embodiment.

  The write processing unit 50 executes a process of writing the data input via the input I / F 40 to the memory 20, and particularly those closely related to the present embodiment include a CLK generation unit 51, a CLK An inversion unit 52, an input data inversion unit 53, and a selector 54 are included.

  The CLK generator 51 generates a CLK (hereinafter referred to as a normal CLK) that is a signal for synchronizing various processes in the packet processor 30. For example, the CLK generator 51 generates a normal CLK shown in FIG.

  The CLK inverter 52 inverts the normal CLK generated by the CLK generator 51 and converts the normal CLK into an inverted CLK. For example, the CLK inversion unit 52 inverts the normal CLK and converts it into the inverted CLK, as shown in FIG.

  The input data inverting unit 53 generates inverted data obtained by inverting the bit sequence of the normal data input via the input I / F 40 and transmits the generated inverted data to the selector 54 described later. For example, when normal data “bit string: 11010” is input, the input data inverting unit 53 generates inverted data “bit string: 00101” (see (A) in FIG. 1-2), and the generated inverted data. “Bit string: 00101” is transmitted to the selector 54 described later.

  The selector 54 combines the synthesized data obtained by combining the normal data input via the input I / F 40 and the inverted data received from the input data inverting unit 53 with the 0 plane 21 of the memory 20 to which the same address is assigned and Separated into one surface 22 and stored. Specifically, the selector 54 stores the normal data of the composite data on the 0 side 21 in accordance with the rising edge of the normal CLK, and stores the inverted data of the composite data on the 1 side 22 in accordance with the rising edge of the inverted CLK.

  For example, when the normal data “bit string: 11010” and the inverted data “bit string: 00101” are received, the selector 54 combines the normal data and the inverted data into the synthesized data “bit string: 101001001” (FIG. 1− 2 (A)). Then, the selector 54 stores the normal data of the composite data in the 0 plane 21 of the memory 20 in accordance with the rising edge of the normal CLK generated by the CLK generator 51. For example, the selector 54 sequentially stores the normal data “bit string: 11010” of the composite data “bit string: 101001001” in the 0 plane 21 in synchronization with the rising edges of the normal CLKs 1 to 5 ((A) in FIG. 1-2). reference).

  Further, the selector 54 stores the inverted data of the combined data on the first surface 22 of the memory 20 in accordance with the rising edge of the inverted CLK in which the normal CLK is inverted by the CLK inversion unit 52. For example, the selector 54 sequentially stores the inverted data “bit string: 00101” of the composite data “bit string: 101001001” on the first surface 22 in accordance with the rising edges of the inverted CLKs 1 to 5 ((A) of FIG. 1-2). reference).

  The read processing unit 60 executes a read process for reading the combined data stored by being separated by the 0 plane 21 and the 1 plane 22, and particularly those closely related to the present embodiment include an FF (flip flop) 61 and , FF 62, 1-plane data reversing section 63, 0-plane detection section 64, 1-plane detection section 65, FF 66, FF 67, selector control section 68, and selector 69.

  Note that FF61, FF62, FF66, and FF67 are logic circuits that can temporarily hold 1-bit information, and perform various processes when the read processing unit executes the read process in synchronization with the rising edge of CLK. To control that.

  The FF 61 reads the normal data of the composite data from the 0 plane 21 in synchronization with the rising edge of the normal CLK. For example, the FF 61 sequentially reads the normal data “bit string: 11010” from the 0 plane 21 in synchronization with the rising edges of the normal CLKs 1 to 5 (see FIG. 1-2B).

  Then, the FF 61 sequentially transmits the 0-plane read data read from the 0-plane 21 to the 0-plane detection unit 64 and the FF 66 described later in synchronization with the next rising edge of the normal CLK. For example, the FF 61 sequentially transmits the 0-plane read data “bit sequence: 11010” to the 0-plane detection unit 64 and the FF 66 described later in synchronization with the rising edges of the normal CLK 2 to 6 ((B) in FIG. 1-2). reference).

  The one-side data inversion unit 63 inverts the bit sequence of the inversion data read out by the FF 62 before being taken into the FF 62. For example, when the FF 62 reads “bit column: 00101” from the first surface 22, the first surface data reversing unit 63 inverts “bit column: 00101” to “bit column: 11010”.

  The FF 62 reads the inverted data of the composite data from the first surface 22 in accordance with the rising edge of the inverted CLK. For example, the FF 62 sequentially reads the inverted data “bit string: 00101” of the composite data from the first surface 22 in accordance with the rise of the inversion CLK1 to 5 (see FIG. 1-2B).

  Then, the FF 62 reads the one-side read data read from the first surface 22 in accordance with the next rising edge of the CLK subjected to the read process, and the first-surface read unit 65 and the FF 67 described later. Send to. For example, the FF 62 sequentially transmits the single-side read data “bit string: 11010” to the single-side detection unit 65 and the FF 67, which will be described later, in accordance with the rising edges of the inverted CLK 2 to 6 (see FIG. 1-2B). ).

  The 0-plane detection unit 64 checks a parity error using a parity bit previously assigned to the 0-plane read data received from the FF 61, and transmits the check result to the selector control unit 68 described later. For example, the 0-plane detection unit 64 checks the parity error of the 0-plane read data “bit string: 11010” and transmits the check result to the selector control unit 68.

  The single-side detection unit 65 checks a parity error using a parity bit previously assigned to the single-side read data received from the FF 62, and transmits the check result to a selector control unit 68 described later. For example, the single-side detection unit 65 checks the parity error of the single-side read data “bit string: 11010” and transmits the check result to the selector control unit 68 described later.

  The FF 66 sequentially transmits the 0-plane read data received from the FF 61 to the selector 69 described later in synchronization with the rising edge of the normal CLK next to the normal CLK for which the parity error check has been performed. For example, the FF 66 normally transmits the 0-plane read data “bit string: 11010” to the selector 69 described later (see (B) of FIG. 1B) in synchronization with the rising edges of the normal CLK 3-7.

  The FF 67 sequentially transmits the one-side read data received from the FF 62 to the selector 69 described later in synchronization with the rising edge of the next inverted CLK after the inverted CLK for which the parity error check has been performed. For example, the FF 67 normally transmits the one-side read data “bit string: 11010” to the selector 69 described later in synchronization with the rising edge of the normal CLK 3 to 7 (see FIG. 1-2B).

  Based on the check results received from the 0-plane detection unit 64 and the 1-plane detection unit 65, the selector control unit 68 controls the selector 69 described later to capture data for which no parity error has been detected. Specifically, as shown in FIG. 3, the selector control unit 68 determines that the 0-plane read data check result is “normal” and the 1-plane read data check result is “normal”. The selector 69 is controlled so as to capture the read data as output data.

  Further, as shown in FIG. 3, the selector control unit 68, when “0 plane: error, 1 plane: normal” or “0 plane: normal, 1 plane: error”, respectively, The selector 69 is controlled so as to take in the normal “1 side” or “0 side” data as output data.

  In addition, as shown in FIG. 3, when both “0” and “1” are “errors”, the selector control unit 68 causes the selector 69 to capture the data of “0” as output data. While controlling, an error signal is output to the output I / F 41.

  For example, in the normal CLK5 parity error check shown in FIG. 1-2B, an error is detected when the fourth bit of the read data read from the 0 plane 21 is changed from “1” to “0”. Suppose that Further, as shown in FIG. 1-2B, it is assumed that no parity error is detected in the parity error check of the inverted CLK5. In the above case, as shown in FIG. 1-2B, the selector control unit 68 normally sets the fourth of the 0-plane read data “bit string: 11000” transmitted from the FF 66 in synchronization with the rising edge of CLK6. The selector 69 is controlled so as not to capture “0”. Then, the selector control unit 68 controls the selector 69 so as to capture the fourth “1” of the one-side read data “bit string: 11010” transmitted from the FF 67 as output data.

  The selector 69 outputs the output data fetched from the FF 66 or FF 67 to the output I / F 41. For example, the selector 69 outputs the output data “bit string: 11010” to the output I / F 41.

[Processing Procedure by Packet Relay Device in First Embodiment]
Next, processing performed by the packet relay apparatus according to the first embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram for explaining the procedure of the writing process by the packet relay device in the first embodiment, and FIG. 5 is a diagram for explaining the procedure of the reading process by the packet relay device in the first embodiment.

[Procedure for Write Processing by Packet Relay Device in Embodiment 1]
As shown in FIG. 4, when packet data (data) is input to the packet relay device 10 according to the first embodiment via the input I / F 40 (Yes in step S101), the input data inverting unit 53 is input. Inverted data is generated by inverting the received data (step S102).

  Then, the selector 54 combines the normal data input via the input I / F 40 and the inverted data generated by the input data inversion unit 53 (step S103).

  After that, the selector 54 stores the normal data of the combined data obtained by combining the normal data and the inverted data in the 0 plane 21 of the memory 20 in accordance with the rising edge of the normal CLK generated by the CLK generator 51 (step S104). ).

  Further, the selector 54 stores the inverted data of the composite data on the first surface 22 of the memory 20 in accordance with the rising edge of the inverted CLK converted by the CLK inverter 52 (step S105), and whether or not an unstored bit remains. Is determined (step S106).

  Here, when an unstored bit remains (Yes at Step S106), the selector 54 returns to Step S104 and stores the normal data of the combined data in the 0 plane 21 in accordance with the rising edge of the normal CLK.

  On the other hand, when there is no unstored bit (No at Step S106), the selector 54 ends the process.

[Procedure for Read Processing by Packet Relay Device in Embodiment 1]
As illustrated in FIG. 5, when the packet relay apparatus 10 according to the first embodiment has reached a predetermined read time (Yes in step S201), the FF 61 displays the normal data of the composite data as 0 in accordance with the rising edge of the normal CLK. 21 (step S202). For example, in the packet relay apparatus according to the first embodiment, when the data is stored in the memory 20 by the writing process, the FF 61 sets the normal data of the composite data to 0 in accordance with the rising edge of the next normal CLK in which the data is stored. Read from 21.

  Then, the FF 62 reads the inverted data of the composite data from the first surface 22 in synchronization with the rising edge of the inverted CLK (step S203). Here, the one-side data inversion unit 63 inverts the inversion data read by the FF 62 before being taken into the FF 62 (step S204).

  Then, the 0-plane detection unit 64 checks the parity error of the 0-plane read data in accordance with the rising edge of the normal CLK next to the normal CLK that has been read by the FF 61 (step S205).

  Further, the single-side detection unit 65 checks the parity error of the single-side read data in accordance with the rising edge of the next inverted CLK after the inversion CLK that has been read by the FF 62 (step S206).

  After that, the selector control unit 68 outputs in accordance with the rising edge of the CLK next to the CLK subjected to the parity check based on the check result of the parity error executed by the 0-plane detection unit 64 and the 1-plane detection unit 65. Data is determined (step S207). Specifically, as shown in FIG. 3, the selector control unit 68 determines that the 0-plane read data check result is “normal” and the 1-plane read data check result is “normal”. Read data is determined as output data.

  Further, as shown in FIG. 3, the selector control unit 68, when “0 plane: error, 1 plane: normal” or “0 plane: normal, 1 plane: error”, respectively, The normal “1 side” or “0 side” data is determined as output data.

  Further, as shown in FIG. 3, when both “0” and “1” are “error”, the selector control unit 68 determines “0” data as output data. Note that the selector control unit 68 outputs an error signal to the output I / F 41 when both “0 side” and “1 side” are “error”.

  Then, the selector control unit 68 causes the selector 69 to take in the output data determined based on the method described above.

  After that, the selector 69 outputs the fetched output data to the output I / F 41 (step S208).

  The above-described procedure is sequentially executed for all the bits of the read data.

[Effect of Example 1]
As described above, according to the first embodiment, the 0 plane 21 and the 1 plane 22 of the memory 20 store data respectively. The read processing unit 60 reads the data stored in the 0 plane 21 in synchronization with the rising edge of the normal CLK and stores it in the 1 plane 22 in synchronization with the rising edge of the CLK having the same rising cycle as that of the normal CLK. Read the stored data. The 0 plane detector 64 checks the parity error of the 0 plane read data read from the 0 plane 21, and the 1 plane detector 65 checks the parity error of the 1 plane read data read from the 1 plane 22. Check. Then, the selector control unit 68 causes the selector 69 to take in data in which no parity error is detected based on the parity error check results of the 0-plane detection unit 64 and the 1-plane detection unit 65. Therefore, it is not necessary to re-read after error detection, and all bits in which an error is detected can be switched to normal bits in the time corresponding to one CLK period after error detection, and accurate read processing can be performed at high speed. It becomes possible.

  Further, according to the first embodiment, the read processing unit 60 reads data stored in the 0 plane 21 in synchronization with the rising edge of the normal CLK, and 1 in synchronization with the rising edge of the inverted CLK obtained by inverting the normal CLK. Data stored in the surface 22 is read out. Therefore, it is possible to execute the process twice in a time corresponding to one CLK period, and it is possible to perform an accurate read process at a higher speed.

  Further, according to the first embodiment, the same address is assigned to the 0 side 21 and the 1 side 22 of the memory 20. Therefore, the two storage areas can be accessed in accordance with the rise and fall of the same CLK, and two data can be read out in a short time.

  Further, according to the first embodiment, the write processing unit 50 writes the normal data to the 0 plane 21 in synchronization with the rising edge of the normal CLK, and writes the inverted data to the 1 plane 22 in synchronization with the rising edge of the inverted CLK. Then, the single-side data reversing unit 63 inverts the single-side read data before checking the parity error by the single-side detecting unit 65, and the single-sided data detecting unit 65 is inverted by the single-sided data reversing unit 63. Check the parity error of the surface read data. Then, the selector control unit 68 causes the selector 69 to take in data in which no parity error is detected based on the parity error check results of the 0-plane detection unit 64 and the 1-plane detection unit 65. Therefore, it is possible to determine the fixed state of the bit that may occur due to an internal failure of the memory as an error, and to immediately notify the administrator of the abnormality of the device.

  Although the first embodiment has been described above, the present invention may be implemented in various different forms other than the first embodiment described above. Therefore, in the following, various different embodiments will be described by being divided into (1) to (3).

(1) Target data In the above-described example, the case where packet data is used as data to be written and read is described. However, the present embodiment is not limited to this. For example, packet data is chain-managed. It is also possible to use a pointer address for this purpose. Hereinafter, an example of a pointer address will be described as a modification. Note that. The pointer address includes data position information in memory and position information of data that is continuous with stored data.

  For example, as shown in FIG. 6, a pointer address “00000000000010100” storing normal data “bit string: 11010” and inverted data “bit string: 00101” is used as target data of the storage device disclosed in the present application. May be.

  That is, the pointer address “00000000000010100” and the inverted pointer address “11111111111101011” obtained by inverting the pointer address may be stored twice in the memory.

  Also by this, for example, even when an error is detected in the reading of the pointer address required every time data is read, all the bits in which the error is detected are set to normal bits in the time corresponding to one CLK period after the error is detected. The packet relay apparatus can be operated without discarding data.

  Further, a parity error can be detected in a bit string in which the bit hardly changes like the upper address of the pointer address, and the bit error is a normal bit string or the bit is fixed due to a component failure or data retention. Can be determined.

(2) Embodiments In the above-described example, the case where the storage device disclosed in the present application is incorporated in a packet relay device has been described. However, the present embodiment is not limited to this example. The case where the storage device disclosed in the present application is incorporated in an arithmetic device or the like may be used.

(3) System Configuration, etc. Further, the processing procedure described in the above embodiment, specific names, information including various data and parameters can be arbitrarily updated unless otherwise specified. For example, in the determination of output data by the selector control unit 68 in the first embodiment, if both the 0-plane read data and the 1-plane read data are errors, the 1-plane read data may be used as the output data.

  Each component of each illustrated device is functionally conceptual and does not necessarily need to be the same as the physically illustrated component. That is, the specific form (for example, the form of FIG. 2) of the distribution / integration of each processing unit and each storage unit is not limited to that shown in the drawing. For example, the input data inverting unit 53 may be built in the selector 54. Further, all or any part of each processing function performed in each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware by wired logic.

  Regarding the embodiment including the above-described embodiment, the following additional notes are disclosed.

(Supplementary Note 1) A storage unit that stores data in each of the first area and the second area;
The data stored in the first area is read in synchronization with the rising cycle of the first clock signal, and is also synchronized with the rising cycle of the second clock signal having the same rising interval as the first clock signal. And a data read processing unit for reading data stored in the second area,
A detection unit for detecting the presence or absence of a parity error for each of the data read by the data read processing unit;
And a data output unit that outputs data on which no parity error has been detected to a predetermined output unit based on a detection result of the detection unit.

(Supplementary note 2) The storage device according to supplementary note 1, wherein the second clock signal is a clock signal obtained by inverting the first clock signal.

(Supplementary note 3) The storage device according to Supplementary note 1 or 2, wherein the same address is assigned to the first area and the second area.

(Supplementary Note 4) The data is written in the first area in synchronization with the rising cycle of the first clock signal, and the inverted data is synchronized with the rising cycle of the second clock signal. A data write processing unit for writing to the second area,
An inversion unit that inverts data read from the second area by the data read processing unit before detecting the presence or absence of the parity error;
The detection unit includes data read from the first area by the data read processing unit and data inverted by the inversion unit after being read from the second area by the data read processing unit. And the detection target of the presence or absence of the parity error,
The storage device according to any one of appendices 1 to 3, wherein the data output unit outputs detection target data for which no parity error has been detected by the detection unit to a predetermined output unit.

(Supplementary Note 5) A storage unit that stores packet data in each of the first area and the second area;
The packet data stored in the first area is read in synchronization with the rising cycle of the first clock signal, and at the rising cycle of the second clock signal having the same rising interval as the first clock signal. A data read processing unit that reads packet data stored in the second area in synchronization with each other;
A detection unit for detecting the presence or absence of a parity error in each packet data read by the data read processing unit;
A packet relay apparatus comprising: a data output unit that outputs packet data for which no parity error has been detected to a predetermined output unit based on a detection result by the detection unit.

10 packet relay device 20 memory 21 0 side 22 1 side 30 packet processing unit 40 I / F for input
41 Output I / F
50 Write Processing Unit 51 CLK Generating Unit 52 CLK Inverting Unit 53 Input Data Inverting Unit 54 Selector
60 Read processing unit 61 FF
62 FF
63 1-plane data reversing section 64 0-plane detection section 65 1-plane detection section 66 FF
67 FF
68 Selector controller 69 Selector

Claims (3)

A storage unit that stores pointer addresses for chain management of packet data in each of the first area and the second area;
Reads the pointer address stored in the first area in synchronization with the rising cycle of the first clock signal and rises the second clock signal having the same rising interval as the first clock signal. a pointer address read processing unit for reading the pointer address stored in the second region is tuned to,
A detection unit for detecting the presence or absence of a parity error of each pointer address read by the pointer address read processing unit;
On the basis of the detection result by the detection unit, memory device parity error is characterized in that and a pointer address output section for outputting a pointer address that was not detected in the predetermined output unit. The pointer address is written in the first area in synchronization with the rising cycle of the first clock signal, and the pointer address obtained by inverting the pointer address is synchronized with the rising cycle of the second clock signal. A pointer address write processing unit for writing to the second area;
An inversion unit that inverts the pointer address read from the second area by the pointer address read processing unit before detecting the presence or absence of the parity error;
Wherein the detection unit includes a pointer address read from said first region by said pointer address read processing section, inverted by the inverting unit to then read out from said second region by said pointer address read processing unit And the detected pointer address as a detection target of the presence or absence of the parity error,
It said pointer address output unit, a storage device according to claim 1, characterized in that the output pointer address to be detected a parity error is not detected by the detecting unit to a predetermined output unit. A storage unit that stores pointer addresses for chain management of packet data in each of the first area and the second area;
Reads the pointer address stored in the first area in synchronization with the rising cycle of the first clock signal and rises the second clock signal having the same rising interval as the first clock signal. a pointer address read processing unit for reading the pointer address stored in the second region is tuned to,
A detection unit for detecting the presence or absence of a parity error of each pointer address read by the pointer address read processing unit;
On the basis of the detection result by the detection unit, the packet relay apparatus, characterized in that a parity error had a pointer address output section for outputting a pointer address that was not detected in the predetermined output unit.

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