JPH0469755A - Information processor - Google Patents

Information processor

Info

Publication number
JPH0469755A
JPH0469755A JP2183036A JP18303690A JPH0469755A JP H0469755 A JPH0469755 A JP H0469755A JP 2183036 A JP2183036 A JP 2183036A JP 18303690 A JP18303690 A JP 18303690A JP H0469755 A JPH0469755 A JP H0469755A
Authority
JP
Japan
Prior art keywords
input
output control
control device
output controller
nak response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2183036A
Other languages
Japanese (ja)
Inventor
Sadanori Yamamoto
山本 禎則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2183036A priority Critical patent/JPH0469755A/en
Publication of JPH0469755A publication Critical patent/JPH0469755A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To execute an exact decision at the time when a fault occurs by detecting a fault of an input/output controller from information for showing its elapsed time, in the case an NAK response is executed by the input/output controller. CONSTITUTION:When an input/output controller 30 becomes a state of executing a negative acknowledge response (NAK response) executed at the time when an I/O instruction cannot be received due to an internal operation, a time counting part 32 is allowed to start a time counting operation. The time counting part 32 outputs the time counting contents to an arithmetic processor 10, and the arithmetic processor 10 receives the NAK response of the input/ output controller 30, and also, decides whether the input/output controller 30 is in the course of internal operation or in the course of hardware fault by comparing data for showing the time counting contents of the time counting part 32 with data given in advance to the inside of the arithmetic processor 10 by a comparing part 11. In such a way, whether the NAK response of the input/output controller 30 is executed due to an internal operation or occurrence of a fault can be decided exactly by the arithmetic processor 10.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置、特に入出力制御装置のハードウ
ェア障害に関して演算処理装置による検出を行う情報処
理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device in which an arithmetic processing unit detects a hardware failure in an input/output control device.

〔従来の技術〕[Conventional technology]

従来の技術によるこの種の情報処理装置は、共通バスに
演算処理装置及び入出力制御装置を接続した情報処理装
置において、入出力制御′装置が内部動8作のために、
ある期間演算処理装置が発行するl/O(入出力)命令
の受付が行えない場合、その間に受信するI/O命令に
対して入出力制御装置が演算処理装置にNAK応答する
ようなハードウェア手段を講じていた。
In this type of information processing device according to the conventional technology, in an information processing device in which an arithmetic processing unit and an input/output control device are connected to a common bus, the input/output control device performs internal operation.
Hardware in which if an I/O (input/output) command issued by an arithmetic processing unit cannot be accepted for a certain period of time, the input/output control unit responds with a NAK to the arithmetic processing unit in response to the I/O command received during that period. He was taking measures.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の技術によるこの種の情報処理装置の問題点は、入
出力制御装置が内部動作のためにハードウェア的にNA
K応答を行った後に入出力制御装置に障害が発生した場
合には永久にN A K応答が行われるため、I/O命
令を発行する演算処理装画側では、入出力制御装置が内
部動作のためにNAK応答を行っているのか、障害が発
生したためにNAK応答を行っているのかを的確に判断
できないという点にある。
The problem with this type of information processing device based on conventional technology is that the input/output control device has a hardware NA due to internal operations.
If a failure occurs in the input/output control device after a K response is issued, the NAK response will be issued forever, so on the arithmetic processing device side that issues the I/O command, the input/output control device will not be able to control internal operations. The problem is that it cannot be accurately determined whether the NAK response is being made because of a failure or because a failure has occurred.

本発明の目的は、上述の従来技術による問題点に対し、
入出力制御装置のNAK応答が内部動作のためのものか
障害発生によるものかを、演算処理装置が的確に判断可
能とすることにある。
An object of the present invention is to solve the problems caused by the above-mentioned prior art.
An object of the present invention is to enable an arithmetic processing device to accurately determine whether a NAK response from an input/output control device is due to an internal operation or a failure.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の情報処理装置は、共通バスに演算処理装置及び
入出力制御装置を接続した情報処理装置において、前記
入出力制御装置が前記演算処理装置からのI/O命令を
内部動作のために受け付けられないときに行う否定応答
(以下NAK応答と言う)を行う状態となったならば計
時動作を開始するハードウェアによる計時手段と、前記
入出力制御装置がN A K応答を行う状態となってか
らの経過時間を示す情報を伴って応答する手段とを有し
、前記演算処理装置は前記入出力制御装置によりN A
 K応答が行われた場合、前記経過時間を示す情報から
前記入出力制御装置の障害を検出する手段を備えて構成
される。
The information processing device of the present invention has an arithmetic processing device and an input/output control device connected to a common bus, wherein the input/output control device receives an I/O command from the arithmetic processing device for internal operation. When a negative response (hereinafter referred to as a NAK response) is made when the input/output control device is unable to respond, the hardware timekeeping means that starts a timekeeping operation and the input/output control device are in a state of making a NAK response. and means for responding with information indicating the elapsed time since N A
The device is configured to include means for detecting a failure in the input/output control device from information indicating the elapsed time when a K response is made.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構成を示すブロック図であ
る。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

入出力制御装置30が内部動作もしくは、ハードウェア
障害でNAK応答を行う状態となったとき、入出力制御
装置30の制御部である入出力制御部33はNAK応答
を行う状態となってからの経過時間を計時する計時部3
2に計時動作を開始させる。
When the input/output control device 30 enters a state in which it makes a NAK response due to an internal operation or a hardware failure, the input/output control section 33, which is the control section of the input/output control device 30, Timing unit 3 that measures elapsed time
2 to start the timing operation.

I/O命令を発行する演算処理装置/Oが入出力制御装
置30に対してI/O命令を発行すると、入出力制御装
置30内部の共通バスとの送受信を行う送受信部31は
、前記I/O命令を受信したことを入出力制御部30に
通知する。
When the arithmetic processing unit/O that issues an I/O command issues an I/O command to the input/output control device 30, the transmitter/receiver 31 that performs transmission/reception with the common bus inside the input/output control device 30 The input/output control unit 30 is notified that the /O command has been received.

入出力制御部30は、NAK応答を行う状態なので、送
受信部31にN A K信号の出力を指示すると同時に
、計時部32に計時内容を演算処理装置/Oに対して出
力するよう指示する。計時部32は計時内容を8ビツト
データとして8ビツトの信号線により演算処理装置/O
に出力する。
Since the input/output control section 30 is in the state of making a NAK response, it instructs the transmitter/receiver section 31 to output the NAK signal, and at the same time instructs the timer section 32 to output the time measurement contents to the arithmetic processing unit/O. The clock unit 32 converts the time measurement contents into 8-bit data and sends it to the arithmetic processing unit/O through an 8-bit signal line.
Output to.

そこで演算処理装置/Oは、入出力制御装置30のN 
A K応答を受け付けると共に、計時部32の計時内容
を表す8ビツトデータと、演算処理装置/Oの内部にあ
らかじめ与えられたデータ(入出力装置30が内部動作
に要する最大時間を表すデータ)とを、比較部11で比
較することにより、入出力制御装置30が内部動作中か
、ハードウェア障害中なのかを判断する。
Therefore, the arithmetic processing unit/O
In addition to accepting the AK response, it also receives 8-bit data representing the time measurement content of the timer 32, data given in advance to the inside of the arithmetic processing unit/O (data representing the maximum time required for internal operation of the input/output device 30). By comparing these in the comparison unit 11, it is determined whether the input/output control device 30 is in internal operation or is experiencing a hardware failure.

N A K応答を行う状態が解除されると、入出力制御
部33は計時部32の計時内容をリセットする。
When the state of performing the NAK response is released, the input/output control section 33 resets the time measurement contents of the time measurement section 32.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入出力制御装置がI/O
命令に対してN A K応答を行った場合に、内部動作
によるものかハードウェア障害によるものかを、演算処
理装置は的確に判断できるという効果がある。
As explained above, in the present invention, the input/output control device
When a NAK response is made to an instruction, the arithmetic processing device can accurately determine whether the problem is due to an internal operation or a hardware failure.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すブロック図であ
る。 /O・・・演算処理装置、11・・・比較部、20・・
・共通バス、30・・・入出力制御装置、31・・・送
受信部、32・・・計時部、33・・・(入出力)制御
部、34・・・内部バス、35・・・計時データ信号線
(8ビツト幅)。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. /O... Arithmetic processing unit, 11... Comparison unit, 20...
- Common bus, 30... Input/output control device, 31... Transmission/reception section, 32... Time measurement section, 33... (Input/output) control section, 34... Internal bus, 35... Time measurement Data signal line (8 bit width).

Claims (1)

【特許請求の範囲】[Claims] 共通バスに演算処理装置及び入出力制御装置を接続した
情報処理装置において、前記入出力制御装置が前記演算
処理装置からのI/O命令を内部動作のために受け付け
られないときに行う否定応答(以下NAK応答と言う)
を行う状態となったならば計時動作を開始するハードウ
ェアによる計時手段と、前記入出力制御装置がNAK応
答を行う状態となってからの経過時間を示す情報を伴っ
て応答する手段とを有し、前記演算処理装置は前記入出
力制御装置によりNAK応答が行われた場合、前記経過
時間を示す情報から前記入出力制御装置の障害を検出す
る手段を備えて成ることを特徴とする情報処理装置。
In an information processing device in which an arithmetic processing unit and an input/output control device are connected to a common bus, a negative response (a (hereinafter referred to as NAK response)
The input/output control device has a hardware timer that starts a timekeeping operation when the input/output control device is in a state to perform a NAK response, and a means for responding with information indicating the elapsed time since the input/output control device became in a state to perform a NAK response. Information processing characterized in that the arithmetic processing unit includes means for detecting a failure of the input/output control device from information indicating the elapsed time when the input/output control device makes a NAK response. Device.
JP2183036A 1990-07-11 1990-07-11 Information processor Pending JPH0469755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2183036A JPH0469755A (en) 1990-07-11 1990-07-11 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2183036A JPH0469755A (en) 1990-07-11 1990-07-11 Information processor

Publications (1)

Publication Number Publication Date
JPH0469755A true JPH0469755A (en) 1992-03-04

Family

ID=16128617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2183036A Pending JPH0469755A (en) 1990-07-11 1990-07-11 Information processor

Country Status (1)

Country Link
JP (1) JPH0469755A (en)

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