JPH04343147A - Interrupt control method - Google Patents

Abstract

PURPOSE:To detect the abnormality of an interrupt request and to facilitate finding of its cause, as to an interrupt control system in which a processor performs the interrupt processing by means of the interrupt signal from an external device. CONSTITUTION:A decoder 4 decoding a status signal indicating the execution state of a processor 2 at a prestage cycle and outputting an interrupt recognition signal when the status signal indicates the execution state of the interrupt processing, and discrimination parts 5 and 6 discriminating whether or not the interrupt signal disappeared when the interrupt recognition signal is outputted from a decoder 4, are provided, and the device is constructed so that the abnormality of the interruption from an external device 1 can be discriminated from the discrimination result.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system. When an interrupt signal is input from an external device, the processor interrupts the program being executed and processes the interrupt using another program. When an abnormality occurs, the processor may not be able to determine whether or not to continue interrupt processing, and the processor may hang up or run out of control. Therefore, it is necessary to be able to automatically determine when an abnormality as described above has occurred and take appropriate measures.

0002

2. Description of the Related Art FIG. 3 is a block diagram illustrating a process in which a processor 2 starts interrupt processing in response to an interrupt request from an external device 1, and FIGS. 4 to 6 are time charts of interrupt processing in conventional examples.

First, an interrupt request signal a output from an external device 1 and an enable signal b for masking the interrupt request signal a are input to an AND gate 3. The output of the AND gate 3 is then input to the processor 2 as an interrupt signal c. As shown in FIG. 4, when the interrupt request signal a and the enable signal b are both "1", the interrupt signal c is sent to the processor 2.

[0004] Upon receiving the interrupt signal c, the processor 2 finishes the execution of the previous cycle and then internally generates a read command for the address where the interrupt processing program is stored and starts interrupt processing. The occurrence of the above-mentioned read command indicates that the processor 2 has recognized that there has been a request for interrupt processing from the external device 1, and the read command generated in this way is recognized as an interrupt processing request. It is used as the signal d, and as shown in FIG. 4, it is generated with a delay from the interrupt signal c.

However, as shown in FIG. 5, even though interrupt processing is started by the interrupt recognition signal d inside the processor 2, the enable signal b sent to the AND gate 3 disappears midway due to noise etc. Shi “1”
When a situation occurs where the signal changes from "1" to "0", the interrupt signal c, which is the output of the AND gate 3, also changes from "1" to "0" at this point. As a result, the processor 2 is placed in a contradictory state in which it has to execute interrupt processing even though there are no more interrupt requests from the external device 1, resulting in a hang-up or runaway. As shown in FIG. 6, a similar situation occurs when the interrupt request signal a changes from "1" to "0".

[0006]

[Problems to be Solved by the Invention] As mentioned above, when an abnormality occurs in the interrupt request signal a or the enable signal b from the external device 1, conventionally there was no means to recognize that an abnormality had occurred. Even if the processor hangs up or runs out of control, it takes time to investigate the cause.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to detect an abnormality in an interrupt request and facilitate investigation of its cause.

[0008]

[Means for Solving the Problem] The above problem is solved by using an interrupt control system that causes the processor 2 to perform interrupt processing in response to an interrupt signal from an external device 1. a decoder 4 that decodes a status signal indicating the interrupt processing and outputs an interrupt recognition signal when the status signal indicates the execution state of interrupt processing; This is achieved by an interrupt control system characterized in that it is provided with determination units 5 and 6 that determine whether or not the external device 1 has disappeared, and that an abnormality in the interrupt from the external device 1 is determined based on the determination result.

[0009]

[Operation] When an interrupt signal is received from the external device 1, the processor 2 interrupts the program being executed and starts processing such as reading the address where the interrupt processing program is stored. On the other hand, the processor 2 generates a status signal indicating the execution state of the previous cycle for debugging purposes at the end of each cycle. Therefore, when receiving an interrupt signal from the external device 1, the processor 2 generates a status signal indicating the execution state of the previous cycle. A status signal indicating the execution status will be generated.

The present invention utilizes the above status signal to determine whether an interrupt signal is abnormal. That is, by decoding the status signal generated by the processor 2 by the decoder 4, it is detected that a status signal corresponding to the start of interrupt processing has been generated, and an interrupt recognition signal is generated. Then, at the time when the interrupt recognition signal is output, it is determined whether an abnormality has occurred in which the interrupt signal input to the processor 2 has disappeared, so the processor hangs up or goes out of control. By referring to the above-mentioned determination result when a problem occurs, it can be easily determined whether or not the cause is an abnormality occurring in an interrupt request from an external device.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram illustrating an embodiment of the present invention, and FIG. 2 is a time chart of the signals shown in FIG. Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

First, the interrupt request signal a and the enable signal b from the external device 1 are sent to the AND gate 3, and when both signals become "1", the interrupt signal c is sent to the processor 2.
is input to.

On the other hand, in each cycle, the processor 2 outputs a status signal STA indicating the execution state in the previous cycle.
T0-2 are generated, and the execution state thereof is shown by the combination of STAT0-2 shown in FIG. For example, if the combination of STAT0-2 is (100),
"pipeline hold mode", (110) indicates "WAIT mode", and (101) indicates "interrupt processing start mode". Therefore, processor 2
When receives the interrupt signal c and starts interrupt processing by issuing a read command for the address where the interrupt processing program is stored, the combination of STAT0 to STAT2 becomes (101
).

Therefore, as shown in FIG.
2 becomes (101), the decoder 4 generates an interrupt recognition signal d. This interrupt recognition signal d is AND
Sent to Gate 5. In addition to the above-mentioned interrupt recognition signal d, a signal -c obtained by inverting the interrupt signal c by the NOT gate 7 is input to the AND gate 5 .

Therefore, the output signal e of the AND gate 5 is:
Interrupt signal c is interrupt request signal a or enable signal b
It disappears due to an abnormality that occurs and changes from "1" to "0",
Further, when the interrupt recognition signal d is generated, it is generated in synchronization with the clock CLK. Signal e is sent to JK flip-flop 6 to invert its output signal f.

As described above, when the interrupt signal c disappears midway due to an abnormality in the interrupt request signal a or the enable signal b, the output signal f of the JK flip-flop 6 is inverted, and as a result, the output signal f from the external device is inverted. It is possible to know that there is an abnormality in the interrupt request.

If the signal f is held in a register (not shown), by referring to it, it becomes easy to investigate the cause when the processor 2 hangs up or goes out of control. Furthermore, the interrupt processing of the processor 2 can be interrupted by resetting the processor 2 using the output signal f.

In the above embodiment, the status signal generated by the processor 2 is decoded to create the interrupt recognition signal d, but the processor 2
It is also possible to use a command signal for reading out the address where the interrupt processing program is stored after receiving the interrupt processing program as the interrupt recognition signal d.

[0019]

[Effects of the Invention] As described above, according to the present invention, if there is an abnormality in an interrupt request from an external device, it can be detected. Beneficial.

[Brief explanation of drawings]

[Fig. 1] Block diagram showing an embodiment of the present invention,

[Figure 2
] Time chart showing an embodiment of the present invention,

[Figure 3]
A block diagram showing the problems of the conventional example,

[Fig. 4] Time chart of interrupt processing according to the conventional example (Part 1),

[Figure 5] Time chart of interrupt processing according to the conventional example (part 2),

[Fig. 6] Time chart of interrupt processing according to the conventional example (part 3),

[Explanation of symbols]

1 External device
4 Decoder 2 Processor
6 flip flop

Claims (1)

[Claims] [Claim 1] In an interrupt control method in which a processor (2) is caused to perform interrupt processing by an interrupt signal from an external device (1), a status signal indicating the execution state of the processor (2) in the previous cycle is provided. a decoder (4) which outputs an interrupt recognition signal when the status signal indicates the interrupt processing execution state;
The device is equipped with a determining unit (5, 6) that determines whether or not the interrupt signal has disappeared at the time when the interrupt recognition signal is output from the decoder (4), and based on the determination result, the external device (1)
) is characterized in that an interrupt control method is characterized in that an abnormality in an interrupt from an interrupt is determined.