JPH08147176A - Illegal interruption request signal detecting circuit - Google Patents

Abstract

PURPOSE: To prevent the malfunction of a processor circuit caused by an illegal interruption request signal to be non-outputted just after being outputted. CONSTITUTION: When an interruption permit signal (e) from a processor circuit 1 is changed, respective interruption request signals (a)-(d) respectively outputted from respective external equipment 21-24 are held in a flip-flop circuit 3 and when the interruption permit signal is outputted corresponding to the outputs of the respective interruption request signals, it is detected whether the interruption request signals are held in the flip-flop circuit 3 or not. When they are not held, it is reported through an interruption terminal NMI of the processor circuit 1 to the processor circuit 1 that the signals are illegal interruption requests. As a result, the malfunction of the processor circuit 1 caused by the illegal interruption request signals can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in a device comprising a processor circuit and a plurality of external devices, detects an illegal interrupt request signal when data is transmitted by sending an interrupt request signal from the external device to the processor circuit. Regarding the detection circuit.

[0002]

2. Description of the Related Art An example of this type of system in which a plurality of external devices and one processor circuit perform data transmission based on an interrupt request signal has a configuration as shown in FIG. In the figure, 1 is a processor circuit, 21 to 24
Indicates external devices, respectively. Here, each external device 21-
The signal lines for transmitting the respective interrupt request signals a to d generated when the data transmission with the processor circuit 1 from the processor circuit 24 are connected to the interrupt input terminals INT0 to INT3 of the processor circuit 1, respectively. In addition, each interrupt request signal a to d
The interrupt enable output terminal INTA (bar) of the processor circuit 1 which generates an interrupt enable signal to the external device 21
Commonly connected to ~ 24.

When the external device 21 needs to send and receive data to and from the processor circuit 1 while the processor circuit 1 is executing a program, the external device 21 sends an interrupt request signal a through the interrupt input terminal INT0. To the processor circuit 1. Then the processor circuit 1
The program being executed is immediately interrupted and interrupt processing is started, and the interrupt enable signal e is output from the interrupt enable output terminal INTA.
Is output. Then, in this interrupt processing, data is transmitted / received to / from the external device 21 via a bus (not shown).

[0004]

However, in such a system, when the external device 21 outputs an interrupt request signal and immediately thereafter the request signal goes out, the processor circuit 1 shifts to interrupt processing. It is not possible to recognize from which external device the interrupt request signal was output. Therefore, in this case, the processor circuit 1
Erroneously recognizes that an interrupt request has occurred from an external device other than the external device 21 and executes an incorrect interrupt process such as performing data transmission / reception process with the external device 22 that does not request data transmission / reception. This causes a problem that normal processing cannot be performed. Therefore, it is an object of the present invention to prevent the processor circuit from malfunctioning due to an illegal interrupt request signal that immediately becomes non-output after being output.

[0005]

In order to solve such a problem, the present invention provides a plurality of external devices and each external device by returning an interrupt enable signal in response to an interrupt request signal output from each external device. And a processor circuit for transmitting data, the first holding means for holding each interrupt request signal output from each external device when the interrupt enable signal changes, and interrupting the output of each interrupt request signal. Detection means for detecting whether or not the interrupt request signal of the first holding means is held when the permission signal is output,
A notifying unit for notifying the processor circuit as an illegal interrupt request according to the non-detection output of the detecting unit is provided. Further, a second holding means is provided for storing each interrupt request signal output from each external device and holding the stored contents until a read operation is performed, and when the processor circuit is notified of an unauthorized interrupt request. To the second
The interrupt request signal is read from the holding means.

[0006]

When the interrupt request signal output from each external device is held in the first holding unit when the interrupt enable signal changes, and when the interrupt enable signal is output from the processor circuit in response to the output of each interrupt request signal Whether or not the interrupt request signal is held in the first holding means is detected, and if it is not held, the processor circuit is notified of the illegal interrupt request. As a result, an unauthorized interrupt request signal that immediately outputs no output after being output from each external device is accurately detected and transmitted to the processor circuit, so that the malfunction of the processor circuit can be reliably prevented. Further, each interrupt request signal output from each external device is individually held in the second holding unit, and when an illegal interrupt request is notified, the processor circuit reads and inputs the contents of the second holding unit. . As a result,
The source of the illegal interrupt request signal can be easily detected.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an illegal interrupt request signal detection circuit according to the present invention. In the figure, 1
Is a processor circuit, and 21 to 24 are external devices, which are similar to the conventional circuit shown in FIG. In addition, in the circuit of this embodiment, the flip-flop circuit (F / F) 3 (first
Holding means), an OR circuit 4 (detecting means, notifying means), flip-flop circuits 5 to 8 (second holding means), a rising detection unit 9, and a register circuit 10.

By the way, in each of the external devices 21 to 24, when transmitting and receiving the data to and from the processor circuit 1, the interrupt request signals a to d are output to the processor circuit 1 to transmit and receive the data. There is. That is,
For example, when the external device 21 needs to send and receive data to and from the processor circuit 1, the external device 21 sends an interrupt request signal a to the processor circuit 1 via the interrupt input terminal INT0. Then, the processor circuit 1 immediately interrupts the main program being executed and starts interrupt processing,
An interrupt enable signal e is output from the interrupt enable output terminal INTA (bar). After that, the processor circuit 1 transmits / receives data to / from the external device 21 via the data bus in the interrupt process, and returns to the main program after the end.

However, if the interrupt request signal a output from the external device 21 immediately becomes non-output, the processor circuit 1 cannot recognize from which external device the interrupt request signal was output. Therefore, if the output interrupt request signal is not held until the processor circuit 1 outputs the interrupt permission signal e, there is a problem that the processor circuit 1 cannot perform normal processing thereafter. Therefore, in the circuit of this embodiment, a malfunction of the processor circuit 1 is prevented by detecting and notifying the processor circuit 1 of an invalid interrupt request signal that is not output until the interrupt enable signal is output.

The operation of the main part of the circuit of this embodiment will be described below with reference to FIG. In FIG. 1, first, in the flip-flop circuit 3, if the interrupt request signals a to d are output from the external devices 21 to 24 when the interrupt enable signal e is output from the processor circuit 1, the interrupt enable signal Each of the interrupt request signals a to d is stored at the falling edge of e (the inverted signal of the inverter circuit 11). Each interrupt request signal stored in the flip-flop circuit 3 is an interrupt enable signal e from the processor circuit 1.
Is output at the rising edge of and is sent to the OR circuit 4.

That is, each of the interrupt request signals a to d is now set to an "H" level signal, and any one of these interrupt request signals is output to the processor circuit 1 and the flip-flop circuit 3 from any external device. If the interrupt enable signal e from the processor circuit 1 falls at this point, this "H" level interrupt request signal is stored in the flip-flop circuit 3. Subsequently, when the interrupt permission signal e rises, the stored "H" level interrupt request signal is sent to the OR circuit 4, and the OR circuit 4 outputs the "H" level signal. Therefore, in this case, since the interrupt request signal is held until the interrupt enable signal e is output, the processor circuit 1 operates normally and performs data transmission with a corresponding external device.

On the other hand, if the output interrupt request signal is not held until the falling edge of the interrupt enable signal e, the "H" level interrupt request signal is not stored in the flip-flop circuit 3. Therefore, even if the interrupt request signal in the flip-flop circuit 3 is read out and sent to the OR circuit 4 at the subsequent rise of the interrupt permission signal e, the output of the OR circuit 4 cannot be maintained at the “H” level and the output from the “H” level Change to "L" level. in this case,
This "L" level signal is output as the alarm signal f to the external alarm terminal ALM (bar), and is also output to the interrupt terminal NMI (non-maskable interrupt) of the processor circuit 1.

As a result, in the processor circuit 1, a signal changing from the "H" level to the "L" level is input to the interrupt terminal NMI, and an illegal interrupt request different from the interrupt process for performing the above-mentioned data transmission. Interrupt processing for detecting a signal is activated. The processor circuit 1 recognizes that an illegal interrupt request signal is output in the activated interrupt process, and in this case, returns to the main program without performing data transmission with an external device.

The interrupt request signals a to d output from the external devices 21 to 24 are stored in the flip-flop circuits 5 to 8 even if the interrupt enable signal e is not output from the processor circuit. Therefore, the processor circuit 1 can recognize from which external device the interrupt request signal is illegally output by reading the storage contents of the flip-flop circuits 5 to 8.

That is, the processor circuit 1 executes a data read command to the register circuit 10 in the interrupt processing by the interrupt signal through the interrupt terminal NMI which recognizes the illegal output of the interrupt request signal. Then, according to this read command, the read signal g of "L" level is output from the read terminal RD (bar) of the processor circuit 1.
Are connected to the flip-flop circuits 5 through 5
8 is output to the register circuit 1 at the falling edge of the read signal g.
Stored at 0.

Each of the flip-flop circuits 5-8
At the same time that the stored contents (that is, the interrupt request signal output from the external device) is accumulated in the register circuit 10, the accumulated contents are processed as an illegal output interrupt request signal h via the data bus by the above-mentioned read signal g as the processor circuit 1 Data terminal DATA. Therefore, the processor circuit 1 can recognize from which external device the interrupt request signal is illegally output by detecting the illegal output interrupt request signal h. When the rising edge detector 9 detects the rising edge of the read signal g, each flip-flop circuit 5 is detected at this rising edge.
Clear the stored contents of ~ 8.

FIG. 2 is a timing chart showing an example of the output timing of various signals output from the respective parts of the circuit of this embodiment which performs the above operation. Based on this timing chart, the operation of the main part of the circuit of this embodiment will be described in more detail. 2A shows the output timing of the interrupt request signal a output from the external device 21.
2B shows the output timing of the interrupt permission signal e output from the processor circuit 1, and FIG. 2C shows the output timing of the interrupt request signal b output from the external device 22.

In the example of FIG. 2, the interrupt request signal a output from the external device 21 is normal because it is held until the interrupt enable signal e is output from the processor circuit 1, but it is output from the external device 22. The interrupt request signal "b" is not held until the interrupt permission signal "e" is output, and thus is an illegal output. Then, in this case, after the interrupt request signal e is output from the processor circuit 1 at a time point, the alarm signal f is output at the time point when the signal e rises at a time point as described above (FIG. 2 (d)).

This alarm signal f is sent to the processor circuit 1
Is also input to the interrupt terminal NMI, and the processor circuit 1 is activated by the alarm signal f to execute interrupt processing. Then, when the read signal g as described above is output in the interrupt processing (FIG. 2E), the illegal output interrupt request signal h stored in the flip-flop circuits 5 to 8 and accumulated in the register circuit 10 is read out. And output (FIG. 2 (f)). As a result, the processor circuit 1 can recognize from which external device the interrupt request signal is illegally output, and therefore the processor circuit 1
Based on this recognition, it is possible to avoid malfunction due to an illegal interrupt request signal.

[0020]

As described above, according to the present invention, each interrupt request signal output from each external device is held in the first holding means when the interrupt enable signal changes,
When the interrupt enable signal is output from the processor circuit in response to the output of each interrupt request signal, it is detected whether or not the interrupt request signal is held in the first holding means, and if it is not held, it is sent to the processor circuit. Since the notification of an illegal interrupt request is made, an illegal interrupt request signal that causes no output immediately after being output from each external device is accurately detected and transmitted to the processor circuit. It can be surely prevented. Further, each interrupt request signal output from each external device is individually held in the second holding means, and when an unauthorized interrupt request is notified, the processor circuit reads the contents of the second holding means. Therefore, the source of the illegal interrupt request signal can be easily detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an illegal interrupt request signal detection circuit according to the present invention.

FIG. 2 is a timing chart showing the operation timing of each part of the circuit of the above embodiment.

FIG. 3 is a block diagram of a conventional circuit.

[Explanation of symbols]

1 ... Processor circuit, 21-24 ... External device, 3,5-
8 ... Flip-flop circuit, 4 ... OR circuit, 9 ... Rise detector, 10 ... Register circuit.

Claims (2)

[Claims] 1. An apparatus comprising a plurality of external devices and a processor circuit for transmitting data to and from each external device by returning an interrupt enable signal in response to an interrupt request signal output from each external device. First holding means for holding each output interrupt request signal when the interrupt enable signal changes, and interrupt request signal of the first holding means when an interrupt enable signal is output for each output of the interrupt request signal An unauthorized interrupt request signal detection circuit, comprising: detection means for detecting the presence or absence of holding of the signal; and notification means for notifying the processor circuit as an unauthorized interrupt request according to the non-detection output of the detection means. 2. The illegal interrupt request signal detection circuit according to claim 1, wherein each interrupt request signal output from each external device is individually stored, and the stored content is held until a read operation is performed. An illegal interrupt request signal detection circuit comprising holding means, wherein the processor circuit reads an interrupt request signal from the second holding means when an illegal interrupt request is notified.