JP2856573B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus, and more particularly to a data transfer apparatus using a broadcast function for simultaneously transferring data from a requester module to each of acceptor modules to be transferred.

[0002]

2. Description of the Related Art Conventionally, in a data transfer apparatus, when data transfer is performed between one requester module and a plurality of acceptor modules, when data is individually transferred from the requester module to each of the plurality of acceptor modules. The requester module outputs a data transfer request signal only to the transfer target acceptor module. When an accept signal is returned from the acceptor module in response to the data transfer request signal, data transfer is started between the requester module and the acceptor module to be transferred.

On the other hand, when performing data transfer using a broadcast function of simultaneously transferring data from the requester module to each of the acceptor modules to be transferred, a common data transfer request signal is output from the requester module to all of the acceptor modules. Is done.
In response to this data transfer request signal, if any one of the acceptor modules prepared by wired connection between the requester module and the acceptor module returns an accept signal, the common accept signal to the requester module becomes active. . As a result, data transfer is started between the requester module and all of the plurality of acceptor modules.

In such a conventional data transfer device, a requester module outputs a data transfer request signal only to an acceptor module to be transferred, and the transfer is performed when an accept signal is returned in response to the data transfer request signal. Data transfer has been started with the target acceptor module. In such a system as described above, data transfer is generally not performed using a broadcast function. Also, when performing data transfer using the broadcast function, if any one of the plurality of acceptor modules returns an accept signal in response to the common data transfer request signal, the common accept signal to the requester module is returned. It becomes active and starts data transfer. In either case, basically, the same data transfer is performed to each of the upsector modules, so that the data transfer is normally performed. However, even if a hardware error occurs in one acceptor module and data transfer in the acceptor module is not ready, if data transfer is performed using the broadcast function, data transfer is normally performed in another acceptor module. On the other hand, there is a problem that data transfer is not performed normally to the acceptor module in which the error has occurred. In this case, there is also a problem that the bus driver operates improperly, causing a bus fight and reducing the reliability of the bus.

[0005] Further, in a data transfer device in which data transfer between the requester module and all of the plurality of acceptor modules is performed only by the broadcast function, there is a problem that individual data transfer to each of the plurality of acceptor modules is not performed.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems of the prior art, and to perform both individual data transfer and data transfer using a broadcast function to a plurality of acceptor modules. It is an object of the present invention to provide a data transfer device capable of performing the above.

[0007]

A data transfer device according to the present invention includes a requester module and a plurality of acceptors connected to the requester module via a data bus and outputting an accept signal in response to a data transfer request signal from the requester module. A data transfer device comprising a module, wherein when the data transfer is performed by using a broadcast function of simultaneously performing data transfer from the requester module to each of the transfer target acceptor modules, from the transfer target acceptor module. Detecting means for detecting that all of the accept signals have been inputted, and detecting the transfer target by the detecting means.
The accept signals from each of the acceptor modules
Means for notifying the detection of an abnormality when not detected
It is characterized by having .

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment of the present invention. In these figures, when data is individually transferred from the requester module 1 to each of the acceptor modules 2 to 4, the requester module 1 outputs data transfer request signals 101 to 103 to the acceptor modules 2 to 4 to be transferred. I do. The transfer target acceptor modules 2 to 4 respond to the data transfer request signals 101 to 103 by accept signals 104 to
Returns 106. As a result, data transfer between the requester module 1 and the acceptor modules 2 to 4 to be transferred via the data bus 100 is started.

On the other hand, when data is transmitted from the requester module 1 to the acceptor modules 2 and 3 among the plurality of acceptor modules 2 to 4 using the broadcast function, the requester module 1 transmits the data transfer request signals 101 and 102. Validate and send a data transfer request to acceptor modules 2 and 3 and bus control circuit 5, respectively.

Acceptor modules 2 and 3 return accept signals 104 and 105 after a certain period of time after receiving data transfer request signals 101 and 102, and report the transfer permission to requester module 1 and bus control circuit 5. At this time, when the requester module 1 detects that the acceptor modules 1 and 2 have returned the accept signals 104 and 105 from all the acceptor modules 2 and 3 to which the data transfer request signals 101 and 102 have been validated, the requester module 1 And the common request signal 107 to the acceptor modules 2 to 4 is validated.

The requester module 1 determines that data transfer has become possible because the common request signal 107 has become valid, and starts sending data via the data bus 100. The acceptor modules 2 and 3 determine that data transfer has become possible because the common request signal 107 has become valid, and start receiving data via the data bus 100. By the above operation, the requester module 1
, Data transfer using the broadcast function to the acceptor modules 2 and 3 is performed.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 4 is a time chart showing the operation of another embodiment of the present invention. In these figures, the requester module 11 to the acceptor modules 12 to 1
In the case where the data transfer is performed individually for each of the requester modules 4, the requester module 11
Data transfer request signals 111 to 113 for 2 to 14
Is output. Acceptor module 12-1 to be transferred
4 returns accept signals 114-116 to the data transfer request signals 111-113. by this,
Data transfer between the requester module 11 and the acceptor modules 12 to 14 to be transferred via the data bus 110 is started. In this case, the data transfer request signals 111 to 113 are invalidated after the accept signals 114 to 116 are returned.

On the other hand, when data is transmitted from the requester module 11 to the acceptor modules 12, 13 among the plurality of acceptor modules 12 to 14 using the broadcast function, the requester module 11 transmits the data transfer request signals 111, 112. Validate and send a data transfer request to acceptor modules 12, 13 and bus control circuit 15, respectively.

The acceptor modules 12 and 13 return the accept signals 114 and 115 after a certain period of time from receiving the data transfer request signals 111 and 112, and report the transfer permission to the requester module 11 and the bus control circuit 15. At this time, when the bus control circuit 15 detects that the requester module 11 has returned the accept signals 114 and 115 from all of the transfer target acceptor modules 12 and 13 which have validated the data transfer request signals 111 and 112, the requester module 11 To enable the acceptance reception detection signal 117 to be accepted.

The requester module 11 determines that data transfer has become possible because the accept reception detection signal 117 has become valid, and the data transfer request signal 111,
At the same time as invalidating 112, data transmission via the data bus 110 is started. The acceptor modules 12 and 13 determine that data transfer has become possible because the data transfer request signals 111 and 112 are invalid and the accept signals 114 and 115 are valid, and start receiving data via the data bus 110. Through the above operation, data transfer from the requester module 11 to the acceptor modules 12 and 13 using the broadcast function is performed.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention, and FIG. 4 is a time chart showing the operation of another embodiment of the present invention. In these figures, the requester module 21 to the acceptor modules 22 to 2
In the case where data transfer is performed individually to each of the acceptor modules 2 to be transferred,
Data transfer request signals 121 to 123 for 2 to 24
Is output. Acceptor module 22-2 to be transferred
4 returns accept signals 124 to 126 in response to the data transfer request signals 121 to 123. by this,
Data transfer is started via the data bus 120 between the requester module 21 and the acceptor modules 22 to 24 to be transferred.

On the other hand, when performing data transfer from the requester module 21 to the acceptor modules 22 and 23 among the plurality of acceptor modules 22 to 24 using the broadcast function, the requester module 21 transmits the data transfer request signals 121 and 122. Validate and send a data transfer request to acceptor modules 22 and 23 and bus control circuit 25, respectively.

At this time, acceptor modules 22 and 2
Since the same request has been issued to No.3, accept signals 124 and 125 should be returned at the same time if the acceptor modules 22 and 23 do not interfere. Therefore, when the bus control circuit 25 detects that the accept signals 124 and 125 are simultaneously returned from all the transfer target acceptor modules 22 and 23 in which the data transfer request signals 121 and 122 are validated, the present invention is applied. In the same processing operation as the embodiment or another embodiment of the present invention,
Requester module 21 and acceptor module 2
Data transfer is performed between the data transfer apparatus 2 and 23.

On the other hand, if the accept signals 124 and 125 are not returned from all of the acceptor modules 22 and 23 at the same time, the bus control circuit 25 sends the abnormality detection report signal 127
And reports the detection of abnormality to the requester module 21. The requester module 21 determines that data transfer has become impossible for some reason because the abnormality detection report signal 127 has become valid, invalidates the data transfer request signals 121 and 122, and interrupts the data transfer process. After that, the requester module 21 detects that the acceptor modules 22 and 23 did not perform the same operation for the same request, and accordingly, the requester module 21 sends the acceptor module 22 or 23 to the host device (not shown).
23 is reported that a hardware error has occurred.

FIG. 7 is a block diagram showing the configuration of still another embodiment of the present invention, and FIG. 8 is a time chart showing the operation of still another embodiment of the present invention. In these figures, when data is individually transferred from the requester module 31 to each of the acceptor modules 32 to 34, the requester module 31 outputs data transfer request signals 131 to 133 to the transfer target acceptor modules 32 to 34. I do. The transfer target acceptor modules 32 to 34 receive the data transfer request signals 131 to
In response to 133, accept signals 134 to 136 are returned. As a result, the data bus 130 is transmitted between the requester module 31 and the transfer target acceptor modules 32-34.
The data transfer is started via.

On the other hand, when data is transmitted from the requester module 31 to the acceptor modules 32 and 33 among the plurality of acceptor modules 32 to 34 using the broadcast function, the requester module 31 transmits the data transfer request signals 131 and 132. Validate and send a data transfer request to acceptor modules 32 and 33 and bus control circuit 35, respectively.

The acceptor modules 32 and 33 return the accept signals 134 and 135 after a certain period of time after receiving the data transfer request signals 131 and 132, and report the transfer permission to the requester module 31 and the bus control circuit 35.

At this time, the acceptor modules 32, 3
Since the same request has been issued to No.3, accept signals 134 and 135 should be returned at the same time if the acceptor modules 32 and 33 do not interfere. However,
For example, in the case of a 1-bit error that occurs when a RAM (random access memory) is accessed by firmware processing or the like in the acceptor modules 32 and 33, a normal operation is performed after executing the 1-bit error collection cycle. Becomes possible. In this case, the timing of returning accept signals 134 and 135 is delayed, but normal data transfer can be performed.

Therefore, when the bus control circuit 35 detects that the accept signals 134 and 135 are simultaneously returned from all of the transfer target acceptor modules 32 and 33 that have enabled the data transfer request signals 131 and 132, Data is transferred between the requester module 31 and the acceptor modules 32 and 33 by using means for temporarily disabling and re-enabling the transfer request signals 131 and 132.

On the other hand, even when the accept signals 134 and 135 are not returned simultaneously so that only the accept signal 134 from the acceptor module 32 is returned, the bus control circuit 35 returns the accept signal 135 for a certain period of time. Wait for coming, then requester module 31
Enables the reception reception signal 137 for accept.

The requester module 31 invalidates the data transfer request signals 131 and 132 when the accept reception detection signal 137 becomes valid, and re-enables only the data transfer request signal 131 for the acceptor module 32 for which the accept signal 134 is valid. Data bus
Data transmission via 130 is started. The acceptor module 32 determines that data transfer is enabled by confirming that the data transfer request signal 131 has been re-enabled, and starts receiving data via the data bus 130. By the above operation, the requester module 3
1 to the acceptor module 32 using the broadcast function.

The requester module 31 reports to the host device (not shown) that the accept signals 134 and 135 have not been returned at the same time, and either cuts off the acceptor module 33 or sends the acceptor module 33 Wait for an instruction to perform data transfer again.

As described above, when the accept signals 104 and 105 are returned from all of the acceptor modules 2 and 3 to be transferred, the common request signal 107 from the bus control circuit 5 to the requester module 1 and the acceptor modules 2 to 4 is enabled. Thus, in the data transfer device capable of individually transferring data from the requester module 1 to each of the acceptor modules 2 to 4, the broadcast from the requester module 1 to the acceptor modules 2 and 3 is enabled by the activation of the common request signal 107. Data transfer using the function becomes possible. As a result, both individual data transfer and data transfer using the broadcast function can be performed for the plurality of acceptor modules 2 to 4.

The acceptor module 1 to be transferred
When the accept signals 114 and 115 are returned from all the devices 2 and 13, the data from the requester module 11 to the acceptor modules 12 and 13 is transmitted in response to the activation of the accept reception detection signal 117 from the bus control circuit 15 to the requester module 11. By disabling the transfer request signals 111 and 112, in a data transfer device capable of individually transferring data from the requester module 11 to each of the acceptor modules 12 to 14, a broadcast function from the requester module 11 to the acceptor modules 12 and 13 is provided. The used data transfer becomes possible. As a result, it is possible to perform both individual data transfer and data transfer using the broadcast function to the plurality of acceptor modules 12 to 14.

Further, when accept signals 124 and 125 from all of the acceptor modules 22 and 23 to be transferred are not returned at the same time, an abnormality detection report signal 127 from the bus control circuit 25 to the requester module 21 is validated and an error is detected. By reporting the detection, the data transfer from the requester module 21 to the acceptor modules 22 and 23 using the broadcast function becomes possible, and the acceptor modules 22 and 23 are transmitted to the host device.
Can report that a hardware error has occurred, preventing the bus driver from operating improperly and preventing bus fights from occurring.
120 can be prevented from deteriorating. As a result, it is possible to perform both individual data transfer and data transfer using the broadcast function to the plurality of acceptor modules 22 to 24.

Furthermore, even when accept signals 134 and 135 are not simultaneously returned from all of the acceptor modules 32 and 33 to be transferred, the bus control circuit 3 waits for the accept signal to return for a certain period of time.
By validating the acceptance reception detection signal 137 from the block 5 to the requester module 31, even in the case of a 1-bit error that occurs when the RAM is accessed, for example, a normal cycle is executed after executing the 1-bit error collection cycle. Since the operation becomes possible, in a data transfer device capable of individually transferring data from the requester module 31 to each of the acceptor modules 32 to 34, in the data transfer device, the requester module 31
Data transfer using the broadcast function to the devices 2 and 33 becomes possible. Thereby, the plurality of acceptor modules 32
34 to both the individual data transfer and the data transfer using the broadcast function can be performed.

In one embodiment, another embodiment, another embodiment, and still another embodiment of the present invention, each data transfer using the broadcast function has been described. Obviously, it is possible to use them in combination, and it is not limited to these.

[0034]

As described above, according to the present invention, when data is transferred from the requester module to each of the transfer target acceptor modules using the broadcast function, the accept signal from each of the transfer target acceptor modules is transmitted. By detecting whether or not all of the acceptor modules have been input, and performing data transfer between the requester module and each of the transfer target acceptor modules at the same time according to the detection result. There is an effect that both data transfer and data transfer using a broadcast function can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a time chart showing the operation of another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 6 is a time chart showing the operation of another embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 8 is a time chart showing the operation of still another embodiment of the present invention.

[Explanation of symbols]

1,11,21,31 Requester module 2-4,12-14,22-24,32-34 Acceptor module 5,15,25,35 Bus control circuit 107 Common request signal 117,137 Accepted reception detection signal 127 Abnormality detection Report signal

Claims (2)

(57) [Claims] 1. A data transfer device comprising: a requester module; and a plurality of acceptor modules connected to the requester module via a data bus and outputting an accept signal in response to a data transfer request signal from the requester module. When the data transfer is performed using the broadcast function of simultaneously performing data transfer from the requester module to each of the transfer target acceptor modules, all of the accept signals from the transfer target acceptor modules are input when the data transfer is performed. a detecting means for detecting that, depending on the detection means
From each of the transfer target acceptor modules.
Abnormal when the accept signal is not detected at the same time
Means for notifying detection . 2. A data transfer device comprising: a requester module; and a plurality of acceptor modules connected to the requester module via a data bus and outputting an accept signal in response to a data transfer request signal from the requester module. When the data transfer is performed using a broadcast function of simultaneously performing data transfer from the requester module to each of the transfer target acceptor modules, the accept signal from each of the transfer target acceptor modules is preset.
Detecting means for detecting that all of the signals have been input within the predetermined time, and detecting the accept signal by the detecting means.
Notify the issued acceptor module to be transferred
Notification means, and the notification content of the notification means
Between the requester module and the accept signal.
Between the output target acceptor module
A data transfer device, wherein the data transfer is performed .