JPS6379444A - Serial data receiver - Google Patents

Abstract

PURPOSE:To improve the reliability by detecting a level of each bit received serially at a prescribed interval and counting number of detected levels existing between 1st and 2nd levels so as to discriminate the level of a reception bit. CONSTITUTION:The level of each bit received serially is detected at a prescribe interval by a level detection means 1 and the number of detected level by the level detection means 1 with respect to each bit in the 1st level and in the 2nd level are counted respectively by a 1st and 2nd counter means 3, 5. A discriminating means 7 discriminates the level reaching earlier a prescribed number in th result of count by the counter means 3, 5 as the level of reception bit.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a serial data receiving device that receives serial data in a data transmission system that serially transmits data using, for example, a home bus system. Regarding.

(Conventional technology) A system that serially transmits data using a home bus system is economically advantageous, but because it uses a ceramic resonator, the clock accuracy is not very good and there are delays and advances. Conventionally, each bit of received data is sampled at the center of the bit and the level of the bit is detected to avoid being affected by the delay or advance. Furthermore, since noise and ringing are generally generated in the path lines of home bus systems, and transmission errors are likely to occur, in order to prevent this, the level of the bit is sampled an arbitrary number of times from near the center of the bit. The process is continued until the same level is detected, and the detected same level is determined as the level of the bit.

(Problems to be Solved by the Invention) As mentioned above, the conventional method of sampling at the center of each bit and detecting the level of that bit has only one sampling point in the center, which is too narrow, There is a problem in that the effects of noise and ringing occurring on the path lines of the system cannot be completely prevented, and transmission errors are likely to occur due to the effects of noise, ringing, etc.

In addition, in the conventional method of determining the level by sampling an arbitrary number of times, the time required to read each bit is not constant, so when trying to perform various other processes in parallel with the data reception operation, processing is subject to time constraints. There is a problem in that it is difficult to perform this simultaneously with data reception.

The present invention has been made in view of the above, and its purpose is to provide a serial data receiving device that can accurately determine the level of received data and perform highly reliable operation. There is a particular thing.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a level detection method that detects the level of each bit received in series at a predetermined interval, as shown in FIG. means 1, and first and second counting means 3, 5 for counting the number of bits whose level detected by the level detecting means is at a first level and the number at a second level, respectively; and determining means 7 for determining the level counted by the counting means for which one of the counting results of the first and second counting means reaches a predetermined number before the other as the level of the received bit. The gist is that.

(Operation) In the serial data receiving device of the present invention, the level of each serially received bit is detected at a predetermined interval, and the number whose detected level is at the first level and the number whose level is at the second level are determined. The level that reaches a predetermined number first among the counting results is determined as the level of the received bit.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a connection configuration diagram of a home bus system to which the serial data receiving device of the present invention is applied, and FIG. 3 is a block diagram showing the configuration of a home bus interface used in the home bus system of FIG. 2. be.

As shown in FIG. 2, the home bus system includes a plurality of home bus interfaces 23 connected to a common data bus 21, and each home bus interface 23 serially communicates data via the data bus 21. There is.

Each home bus interface 23 performs data transmission/reception operations with other home bus interfaces 23 via a serial I10 interface 25 connected to the data bus 21, as shown in FIG.

A CPU 27 consisting of a microprocessor or the like and an interrupt control device 35 are connected to the serial I10 interface 25. A switch 29, a relay 31, and a display device 33 are connected to the CPU 27 via the same bus, and a storage device 41, a control circuit 39 including another CPU, etc., and a timing control device 37 are connected to each other via independent buses. It is connected. In addition, interrupt system till system M
35 is the CPU2 so that an interrupt can be applied to the CPU27.
7 is connected. Furthermore, a ceramic resonator 43 is connected to the CPL 127, thereby obtaining a predetermined clock signal.

Next, the operation of this embodiment will be explained according to the flow shown in FIG.

Normally, the CPU 27 has a serial I10 interface 25.
The switch 29 and the relay 31 control the exchange of data with the home bus interface 23 via the
The control of the display device 33 and the exchange of data with the storage device 41 and control circuit 39 are controlled by interruption. Parallel processing is performed simultaneously by the II device @35 and the timing control device 37.

In such a state, suppose that data having a received waveform as shown in FIG. 5 is first sent from the home bus interface 23 to the home bus interface 23 shown in FIG. 3 via the data bus 21. The data is received via the serial I10 interface 25, and at the rising edge of the start bit of each byte constituting the data, an external interrupt is generated from the interrupt controller 35 to the CPU 27, and the external interrupt shown in FIG. Interrupt processing is started.

Note that in the serial data receiving device of this embodiment,
The level of each bit of the received data is detected at a predetermined interval, and the number of detection levels at a first level, e.g., the rOJ level of a logic level, and the number at a second level, e.g., a logic "1" level, are detected. I am counting. Therefore, in this embodiment, the first counter n counts the number of the first level.

and a second counter n1 counting the number of second levels.
is configured by, for example, software. Then, the level counted by the counter whose counting result reaches the predetermined number N first is determined as the level of the received bit.

Therefore, when an external interrupt occurs and the process shown in FIG. 4(a) is activated as described above, in the process shown in FIG. 4(a), the first counter n (and
The counter n1 of each is cleared to "0" (step 110). Then, in order to use a timer interrupt to perform level detection at the above-described predetermined intervals, the timing for applying the timer interrupt is set (step 120). Note that this timer is configured by, for example, software.

When the timer interrupt timing is set, timer interrupt permission is set, and then external interrupts are disabled during this time (steps 130 and 140), and the original routine is returned to the interrupt processing shown in FIG. 4(a). end. Note that timer interrupts are issued at equal intervals of 2N for each bit.
-1 times (N=1.2...), and the level of the received bit is detected every time this interrupt occurs.

When the timer interrupt set by the process in Figure 4(a) occurs, the timer interrupt process in Figure 4(b) is started and first reads the received data, that is, the bit, and detects the level of the bit. , it is checked whether the level of the received bit is rOJ (step 21
0.220>.

When the level of the received bit is rOJ, the first counter nQ is incremented, and it is checked whether the count result of the first counter nO has reached a predetermined number N (steps 230, 240>. Similarly, when the level of the received bit is "1", the second counter n1 is incremented, and it is checked whether the count result of the second counter n1 has reached a predetermined number N (step 235. 245
).

If the counting results of the first counter n,) and the second counter 0 do not both reach the predetermined number N, the timer interrupt timing is set again as described above (step 290), FIG. The timer interrupt processing in (b) ends. Then, when the interrupt timing set in step 290 comes, the timer interrupt shown in FIG. 4(b) occurs again, and the same operation is repeated.

As a result of this repeated operation, when the count result of the first counter nQ reaches the predetermined number N first, the level of all received bits is determined to be "0" (step 250). Furthermore, when the count result of the second counter n1 reaches the predetermined number N first, the level of the received bit is determined to be "1" (step 2
55).

When the level of the received bit is determined in this way, the first counter nQ and the second counter n1 are cleared to rOJ (step 260). This operation is repeated for each byte for each bit, and when the processing for that byte is completed, step 270, 280) of returning the external interrupt to the enabled state terminates the interrupt processing of FIG. 4(b).

Note that the process in Figure 4(b) is executed every time a timer interrupt occurs, but the process in Figure 4(b) is executed every time a timer interrupt occurs.
), for example, the switch 29.) as described above. Processing such as controlling the relay 319 and display device 33 is performed in parallel in a time-sharing manner (step 310), improving processing performance.

Moreover, the above sampling is performed at a maximum of 2N for each bit.
If the transmission conditions are good, the bit level is determined by sampling N times, so the processing time for N-1 out of 2N-1 times can be used for other parallel processing. , CPU processing time can be used effectively.

Now, when data having a waveform as shown in FIG. 5 is received, the level of each bit of the received data is detected at the timing t01 as shown in the figure. t02. t03
1tj1. Assuming that the detection is performed three times for each bit at t12""", the result of detecting the level of the received bit at that timing will be the level shown as the sample value for each timing in the display of FIG. , N1-J for the stop bit, roO-J for the start bit, rlolJ for data bit 0, and rooOJ for data bit 1. These detected levels are as described above. If the predetermined number N in this case is "2", the received data will be counted as "2" for the stop bit as shown in the table.
1”, “O” for start bit, “1” for data bit O, “0” for data bit 1
, that is, the data value "1010" indicated by *1 in the table
This matches the transmitted data r1010J, but when sampling once near the center of each bit as in the past, the value of the received bit occurs almost at the center of data bit O, as shown by *2. The influence of noise cannot be prevented, and the level of the data bit O is erroneously determined to be "0". Note that the timing t03. marked with *3. Since the value of the bit has already been determined at t13 and the like, sampling is not performed.

[Effects of the Invention] As explained above, according to the present invention, the levels of each of the serially received pins 1 to 1 are detected at predetermined intervals, and the number of the levels at the first and second levels is counted. Since the level that reaches a predetermined number first among the counting results is determined as the level of the received bit, malfunctions due to noise, ringing, and delay or advance of bit timing are prevented, and the level of the received bit can be counted. Since the maximum reception processing time is limited until one of them reaches a predetermined number, even processes with time constraints can be processed in parallel, and processing efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram corresponding to claims of the present invention, FIG. 2 is a connection configuration diagram of a home bus system to which the serial data receiving vj device of the present invention is applied, and FIG. 3 is a serial data receiving diagram according to an embodiment of the present invention. A block diagram of the home bus interface including the device, FIG. 4 is a flowchart showing the operation of the device in FIG. 3, FIG. 5 is a diagram showing an example of the waveform of received data, and FIG. 3 is a table showing level determination results for bits. 1...Level detection means 3...First counting means 5...Second counting means 7...Determination means Figure 1 Figure 1 drawing L (No change in content) Figure 3 Procedure... 1E9i4' (Method) Month, Year, 1986

Claims (1)

[Claims] level detection means for detecting the level of each bit received in series at predetermined intervals; and a number of levels detected by the level detection means for each bit at a first level and a number at a second level. 1st and 2nd counting respectively
and determining that the level counted by the counting means in which one of the counting results of the first and second counting means reaches a predetermined value before the other is determined as the level of the received bit. 1. A serial data receiving device comprising: means.