JPH0646736B2 - Communication failure detection method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication failure detection method, and more particularly to a communication failure detection method when a communication failure occurs in a bus connection type, and more specifically, storage control. The present invention relates to a communication failure detection method suitable for application in communication between a processing device and a channel device in a processing system of a standard method.

[Conventional technology]

In a system having a processing device and a channel device controlled by this processing device, both of which are connected in a bus form and communicate via a bus, to know the presence or absence of communication failure is
It is necessary to achieve stable communication.

Conventionally, this kind of failure detection has adopted a soft timeout method. That is, the communication failure detection method according to this method counts the timing that exceeds the maximum time until the response to the activation from the processing device as a timeout value, and if there is no response within a predetermined timing, there is a failure. Is determined. Such a conventional technique will be described with reference to FIG.

FIG. 4 shows a general block configuration diagram of the processing system of the bus connection type as described above, and FIG. 5 and FIG.
The figure shows an example of a communication sequence.

As shown in FIG. 4, in this system, a processing device 1 and a plurality of channel devices 2 controlled by the processing device 1 are provided.
, 4, ... Are connected in a bus form, and communication is performed via the bus 5.

Communication with each channel device 2, 3, 4, ... Is performed as follows.

First, it is assumed that the processing device 1 activates the channel device 2. Then, the channel device 2 starts the operation according to the instruction content. When the operation is completed, the channel device 2 sends a completion report to the processing device 1 (sequence of FIG. 5). At this time, since the capacity of the processing device 1 is usually large, the processing device 1 has a plurality of channel devices 2, 3, 4, ...
, While each channel device 2, 3, 4, ... Controls a significantly slower IO (input / output device), a method of reporting as soon as the operation is completed is adopted.
Note that, as shown in the sequence of FIG. 6, there is also a sequence in which the activation acceptance for the confirmation of the normality of the communication is immediately accepted, and the report acceptance is immediately accepted for the report.

In this way, communication is performed via the bus 5, and when communication failure due to bus failure or the like occurs, a timing value obtained by adding a margin to the maximum operation time of the slowest IO connected to the channel device is set as a timeout value If the response did not come back even after exceeding the value, it was said that there was a problem.

[Problems to be solved by the invention]

However, such a communication failure detection method has the following drawbacks such as lack of speed of failure detection.

In the above-mentioned conventional method, the IO with the slowest timeout value
Since there is a limit on the maximum time, the time-out value set in advance for determining the presence / absence of a fault becomes large, and as a result, fault detection is delayed. Furthermore, in the system debug stage, waveforms are observed using an analyzer to pursue the cause of communication failures due to design mistakes. In this case, since failure detection (timer overflow) is triggered, the timeout value is large. Then, there is a drawback that the waveform at the time of actually trying to communicate cannot be observed.

The object of the present invention is to detect a communication failure at an early stage,
It is to provide a communication failure detection method that can smoothly perform this even when pursuing the cause of a failure.

[Means for solving problems]

The present invention relates to a communication failure detection method in a processing system in which a processing device and a plurality of channel devices controlled by the processing device are connected in a bus format, and communication is performed via the bus. Individual lead wires are connected between the channel devices, and during communication processing of the report from the channel device to the processing device, the channel device sends a predetermined signal to the individual lead wire between the processing device and the communicating channel device to process. The device is characterized in that a communication failure is detected by comparing the state of the presence / absence of communication via the bus with the state of a predetermined signal on the individual lead wire.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, the processing device 1 includes a communication transmitting / receiving circuit 12, while the channel devices 2, 3, 4, ... Have communication transmitting / receiving circuits 21, 31, 41 ,. , Are connected by a bus circuit 5.

Further, the processing device 1 and the channel devices 2, 3, 4, ... Controlled by the processing device 1 are connected to individual lead wires separately from the bus.
l ₁ , l ₂ , l ₃ , ... are connected, and channel devices 2, 3, 4,
During communication of the report from the processor to the processor 1 via the bus, the communication transmitter / receiver circuit in each channel device turns on the corresponding lead wire so that the individual lead wire between the processor devices 1 is turned on in the communicating channel device. It is designed to control the sending information of.

On the other hand, the processing device 1 has a fault detection circuit 11 as a circuit for comparing and detecting the presence / absence of communication via the bus and ON / OFF of individual lead wires.

The fault detection circuit 11 is a communication transmission / reception circuit in the processing device 1.
12 and the lead lines l ₁ , l ₂ , l ₃ , ... are connected to the communication transmitter / receiver circuits 21, ₃₁ , 41, ... on each channel device side, and a bus communication failure is detected and an error is displayed. I do.

FIG. 2 shows a specific example of the fault detection circuit 11, 111 is an AND logic, 112 is an inverter logic, and 113 is an OR logic.

As described above, in the communication failure detection method shown in FIGS. 1 and 2, the processing device 1 and the plurality of channel devices 2, 3, 4, ... Controlled by the processing device 1 are connected in a bus form. In addition, in the system which communicates via this bus, the individual lead wires l ₁ , l ₂ , l ₃ , ... are connected between the processing device 1 and the channel devices 2, 3, 4 ,. During communication processing for reporting from 2, 3, 4, ... to the processing device 1, the individual lead wires between the processing devices 1 and the communicating channel devices are turned on, and the processing device 1 side receives communication via the bus and individual reading. Bus communication failure is detected by comparing ON / OFF of the lines.

Next, regarding the operation by the configuration of FIG. 1 and FIG.
The communication sequence example shown in the figure will also be described.

In the following, the case of communication between the processing device 1 and the channel device 2 is taken as an example.

First, the processing device 1 is connected to the channel device 2 via the bus circuit 5.
To start. The channel device 2 controls the subordinate IO, and when the operation is completed, communicates a report to the processing device 1 via the bus circuit 5. At this time, the individual lead wire l ₁ is also turned on at the same time (dotted line display portion in FIGS. 1 and 3).

On the other hand, the processing device 1 compares the ON information of the individual lead wire l ₁ with the presence / absence of communication via the bus circuit 5, and displays a fault when a communication fault is detected.

That is, it is turned on from the channel device 2 on the lead wire l _1.
Since the information is sent, the input applied to the fault detection circuit 11 via the lead wire l ₁ is in the high level state, and the above-mentioned report communication is performed from the channel device 2 via the bus circuit 5. Communication unit of the processing device 1
If the information indicating “reported” is given as a high level signal from 12 to the fault detection circuit 11, the output of the fault detection circuit 11 becomes low level, and therefore no error is displayed.

On the other hand, if the ON information is input via the lead wire l ₁ , the high level signal indicating "reported" is not input to the failure detection circuit 11 from the communication transmission / reception circuit 12 side. In this case, as a result of inverting the input from the communication transmitting / receiving circuit 12 and the logical sum output of the lead lines l ₁ , l ₂ , l ₃ , ..., the output of the fault detection circuit 11 becomes high. The level will be displayed and an error will be displayed. That is, it is detected and displayed that the bus circuit 5 has a communication failure.

The communication between the processing device 1 and the channel devices 3, 4, ... Is performed according to this, and if there is a communication failure, this can be detected quickly. Further, since it is possible to eliminate the delay in failure detection as in the past, it is possible to smoothly pursue the cause of a communication failure in the system debugging stage.

〔The invention's effect〕

As described above, according to the present invention, an individual lead wire is connected between a processing device and a channel device, and a signal is sent to the individual lead wire during communication, whereby a bus failure can be detected early. Further, even when the cause is sought in the step of confirming the erroneous function of the hardware including the bus circuit, it is easy to observe the waveform by using the failure display as a trigger, and the cause can be sought smoothly. It goes without saying that the case of detecting the activation failure from the processing device to the channel device can be similarly performed.

[Brief description of drawings]

 FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the fault detection circuit, FIG. 3 is a diagram showing a communication sequence example, and FIG. 4 is a conventional example. FIG. 5 is a block diagram, FIG. 5 is a diagram showing a communication sequence example of a conventional example, and FIG. 6 is a diagram showing another communication sequence example. 1-Processor 2, 3, 4-Channel device 5-Bus circuit 11-Fault detection circuit 12,21,31,41-Communication transceiver circuit 111-AND logic 112-Inverter logic 113 …… or logic

Claims (1)

[Claims] 1. A communication failure detection method in a processing system in which a processing device and a plurality of channel devices controlled by the processing device are connected in a bus format, and communication is performed via the bus. An individual lead wire is connected between each channel device, and during the communication processing of the report from the channel device to the processing device, the channel device sends a predetermined signal to the individual lead wire between the processing device and the communicating channel device, A communication failure detection method characterized in that the processing apparatus detects a communication failure by comparing the status of the presence or absence of communication via a bus with the status of a predetermined signal on the individual lead wire.