JPS63282848A - Interruption signal communication system - Google Patents

Abstract

PURPOSE:To recognize an interruption factor only by the communication line without providing individual lines corresponding on respective interruption factor or complex hardware by dividing one interruption signal line time- divisionally into time slots synchronizing with system clocks and asigning the time slots to respective factors. CONSTITUTION:A CPU sends a start bit 12, counts up time slot number by means of a counter 23 similarly to an interruption sender and shifts the counted number to a shift register 24. At the time of detecting that the slot number counted by the counter 23 exceeds a maximum value, the output of the shift register 24 is inputted to a register 25. At that time, the output of the register 25 holds the interruption signal state of each interruption factor. Then, a start bit sending circuit 21 counts a fixed time and sends the succeeding stat bit 2 again. Consequently, an interruption can be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt signal communication system for a central processing unit of an information processing device.

[Prior Art] Conventionally, methods for communicating this type of interrupt signal include a method in which each interrupt requester individually connects an interrupt request line to a central processing unit and requests an interrupt individually through this signal line;
Wiring multiple interrupt requests to one interrupt request line
There was a method in which all requests were transmitted to the central processing unit as an OR connection. In the latter method, the central processing unit communicates with all requesters to identify the interrupt requester, or has the interrupter send the cause of the interrupt via a data bus, etc. The interrupt requester was identified.

[Problems to be solved] In the conventional interrupt signal communication method described above, if the interrupt request lines are connected individually, one signal line is required for each interrupt cause, which makes it difficult to communicate when there are many causes. The disadvantage is that the amount of wiring increases.

In addition, if multiple factors are combined into one wire by wired OR, the central processing unit that receives this interrupt request checks all the factors to see if each factor has occurred in order to identify the interrupt factor. Alternatively, it is necessary to perform processing such as requesting all requesters to output the interrupt cause to the data bus or address bus. This method requires large hardware and software to identify the cause, and problems remain in terms of cost and processing speed.

[Means for Solving the Problems] The interrupt signal communication system of the present invention, which solves the problems of the conventional methods, can be used in systems where multiple interrupt requests are connected to one interrupt request line. A time slot synchronized with the system clock is provided, and this time slot is assigned to each requester.When each requester requests an interrupt and its own time slot arrives, the interrupt request is placed on the time slot, and the central processing unit The interrupt requester is identified based on the presence or absence of an interrupt request.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a control circuit within a central processing unit that implements an interrupt signal communication method according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a separate sending circuit, and FIG. 3 is a timing chart of a signal communication method.

The control circuit that realizes the interrupt signal communication system of the present invention includes a start bit sending circuit 21 and an interrupt request identification circuit 22.
The start bit sending circuit 21 includes counters 23, 23, and the interrupt request identifying circuit 22 includes a shift register 24.24 and a register 25.25. 1. The interrupt sending circuit in Figure 2 is
This is a circuit for each interrupt requester to detect a time slot and send an interrupt, and includes an own slot comparison circuit 31 and an oven collector driver 32.

Next, the operation will be explained based on the timing chart of FIG. System clock 1 is a clock signal supplied to the entire system, but it may be another clock for interrupt signals. Interrupt request signal 2 is an interrupt request signal connected to each interrupt requester and the central processing unit receiving the interrupt. This interrupt request signal 2 is synchronized with the system clock 1, and all states are sampled at the rising edge of the clock. Start bit 12 is a start bit indicating that time slot 11 is generated from the next clock, and is output from the central processing unit as synchronization start bit 3.

When the start bit 11 is output, each interrupt requester enables the time slot detection enable signal 9 and sets the number of clocks to QA4, QB5, . Start counting like QC6, QD7. QA4 at this time. QB5. QC6,Q
D7 will indicate the current time slot number. Each interrupt requester compares this slot number with the assigned slot number using the own slot comparison circuit 31. If they match, the own time slot detection signal 8 becomes active and the interrupt signal 2 is set to a low level by the open collector driver 32. and notifies the central processing unit that there is an interrupt request. Furthermore, if the number of time slots exceeds the allocated number, the time slot detection enable signal 9 is disabled and the next start bit is waited for.

After sending out the start bit 12, the central processing unit counts the time slot number with the counter 23 and simultaneously shifts it to the shift register 24 in the same way as the side sender. When it is detected that the slot number counted by the counter 23 exceeds the maximum number, the output of the shift register 24 is taken into the register 25. At this time, the output of the register 25 holds the state of the interrupt signal of each interrupt factor.

Thereafter, the start bit sending circuit 21 measures a certain period of time and sends out the next start bit 12 again. By repeating this, interrupts can be recognized.

[Effects of the Invention] As explained above, the present invention divides one interrupt signal line into time slots synchronized with the system clock and allocates the time slots to each factor, thereby providing an individual interrupt signal corresponding to each interrupt factor. This has the effect of being able to recognize an interrupt cause using a single communication line, without requiring communication or complicated hardware to know the cause of the interrupt.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a control circuit within a central processing unit necessary to realize the interrupt signal communication method of the present invention, Fig. 2 is a circuit diagram of an interrupt sending circuit, and Fig. 3 shows an interrupt signal communication method. This is a timing chart. 21 NIST bit sending circuit 22; Interrupt request identification circuit 23: Call name 24: Shift register 25: Register 31: Own slot comparison circuit

Claims (1)

[Claims] In a system where multiple interrupt requests are connected to one interrupt request line, a time slot synchronized with the system clock is provided on the interrupt request line, and this time slot is assigned to each requester, and each requester requests an interrupt. An interrupt signal communication method characterized by placing an interrupt request on the time slot when the current time slot arrives, and the central processing unit identifying the interrupt requester based on the presence or absence of an interrupt request within the time slot.