JP2869971B2 - Failure detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] In the present invention, a storage device, a central processing unit, and a channel device are duplicated, and a plurality of input / output control devices are connected to an input / output bus of the channel device. Information processing system. 2. Description of the Related Art Conventionally, a failure matching method between two central processing units has been used for failure detection in this type of information processing system. In particular, in a system that requires high reliability and early detection of a failure, the matching is performed between the central processing unit and the channel device. FIG. 4 is a block diagram of the information processing system of the above-described failure detection method. This information processing system includes main storage devices 100 and 200, central processing units 101 and 201, channel devices 102 and 202, an input / output bus 103,
The system includes 203, matching circuits 300 and 301, input / output control devices 400 and 401 (for example, a magnetic tape control device and a magnetic disk control device), and input / output devices 450 and 451 (for example, MTU and DKU). The two central processing units 101 and 201 have a master-slave relationship. The master-slave relationship is called a processor mode. The main central processing unit is called an act system or a self system, and controls the entire system. The ACT central processing unit changes the processor mode and the input / output control units 400 and 401
Can be operated. The subordinate central processing unit is called a standby system or another system.
0,401 cannot be operated. The act central processing unit can set or cancel the collation mode of both central processing units 101 and 201. The collation mode is also called a synchronous mode. The state in which the collation mode is released is called a separate mode. In the matching mode, the central processing units 101 and 201 and the channel devices 102 and 202 perform exactly the same processing. Further, in the collation mode, the input / output control devices 400 and 401 operate in accordance with the input / output bus signals from the act channel device, and
To return the operation result. As a result, it is possible to perform collation between the central processing units 101 and 201 and between the channel devices 102 and 202, respectively. On the other hand, in the separate mode, the central processing units 101 and 201 and the channel devices 102 and 202 perform different processes. In the separate mode, the input / output controller 400,
The 401 starts operation according to the signals on the input / output buses 103 and 203 regardless of the processor mode (act type or standby type), and returns the operation result only to the activated input / output bus. The use contention prevention of the input / output control devices 400 and 401 is performed between the central processing units 101 and 201. In this information processing system, between the central processing units 101 and 201 and channel devices 102 and 2
The collation is performed between the 02 by the collation circuits 300 and 301, respectively. In the collation between the central processing units 101 and 201, computation data or computation results are collated. In the collation between the channel devices 102 and 202, collation of processing data in the channel devices 102 and 202, transmission data to the input / output control devices 400 and 401, or reception data from the input / output control devices 400 and 401 is performed.
The collation operation is started when the act central processing unit sets the mode of both central processing units 101 and 201 to the collation mode. These checking operations are performed at the clock level, that is, every operation cycle. [Problems to be Solved by the Invention] In the conventional information processing system described above, the matching is performed every operation cycle. To match the matching results, one central processing unit and the other central processing unit are clocked. It is necessary to synchronize at the level, and the same applies to the channel device. For this reason, the clock of one central processing unit (for example, an act system) is distributed to the other central processing unit (for example, a standby system), or both are distributed. There is a disadvantage that the design must take into account the clock delay between the central processing units, and the input / output control unit has both input / output buses. It is necessary to determine whether to output the operation result to the input / output bus or to output the operation result only to the input / output bus that has been activated, which makes the control complicated. There are drawbacks. [Means for Solving the Problems] The fault detecting device according to the present invention comprises: a first FIFO memory; and a write / connect bus for connecting each input / output bus to a duplicated channel device and the first FIFO memory. When a signal output from the input / output control device is input to the first connection bus and the second connection bus for reading and the act-related channel device operating in the matching mode, the signal is transmitted to the first connection bus. First writing means for writing to the first FIFO memory via the connection bus, and outputting a signal indicating the fullness when the first FIFO memory is full; By inputting the data, the standby channel device operating in the collation mode puts its input / output bus into a data input state, thereby reading data from the first FIFO memory and reading the data from the standby FIFO via the second connection bus. First reading means for outputting to the input / output bus, a second FIFO memory, a third connection bus for connecting the act-related input / output bus and the second FIFO memory, and an act operating in the verification mode. When a signal is output from the channel device of the system to the input / output control device, the signal is converted to the third signal.
Write to the second FIFO memory via the connection bus of
A second writing unit that outputs a signal indicating that the FIFO memory is full; a third FIFO memory; a fourth connection bus that connects the standby I / O bus to the third FIFO memory; The signal output from the standby channel device operating in the collation mode to its input / output bus is written to the third FIFO memory via the fourth connection bus, and when the third FIFO memory is full, the signal is filled. A third FIFO memory, a second FIFO memory, a second FIFO memory, a second FIFO memory, and a second FIFO memory. There is a matching means for comparing the output data of the memory with the output data output from the third FIFO memory and outputting a match or mismatch signal. [Operation] By the same operation performed by the duplicated processing system in the collation mode, the input data of the act system is written through the first FIFO memory, and the data is read out by the data input signal of the standby system to read the data. The data storage state in the first FIFO memory is monitored, and the data output from the channel devices of the respective systems are separately written into the second and third FIFO memories provided for the respective systems, and the data is compared. ,And,
By monitoring the stagnant state of data in each FIFO memory and detecting faults in both systems, synchronization of the operations of both systems is not required, and the I / O controller operates on the activated system. The circuit can be simplified because it only needs to return the result. Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an information processing system provided with an embodiment of a failure detection device according to the present invention. The storage devices 1, 11 are connected to central processing units 2, 12, the central processing units 2, 12 are connected to channel devices 3, 13, respectively, and the input / output buses 4, 14 are connected to the channel devices 3, 13, respectively. ing. The input / output buses 4 and 14 are connected to a failure detection device 30, an input / output control device 20 (for example, a magnetic tape control device), and a 22 (for example, a magnetic disk control device). Signal lines 31, 32, and 33 from the failure detection device 30 are connected to the central processing units 2 and 12, respectively. These two central processing units 2 and 12 have a master-slave relationship. The main central processing unit is called an active (act system or own system) central processing unit, and controls the overall system. The act central processing unit can change the processor mode or operate the input / output control units 20 and 2 regardless of the collation mode.
2 can work. The subordinate central processing unit is called a standby type (SBY or other type) central processing unit. The standby central processing unit changes the processor mode.
2 can not work. The standby central processing unit can operate the input / output control device only in the separate mode. The act central processing unit can also set or cancel the collation mode of both central processing units 2 and 12. The collation mode is also called a synchronous mode. The state in which the collation mode is released is called a separate mode. In the collation mode, the central processing units 2 and 12 and the channel devices 3 and 13 perform the same operation within a certain allowable range, and collate processing results. In the case of the collation mode, the input / output control devices 20 and 22 operate according to the input / output bus signal from the channel device on the act side, and return the operation result to the input / output bus on the act side. On the other hand, in the separate mode, the two central processing units 2 and 12 and the two channel devices 3 and 13 perform different processes, and the processing results are not collated. In the separate mode, the input / output control device starts the operation in accordance with the instruction signal on the input / output bus irrespective of the action and the standby, and returns the operation result only to the activated input / output bus. The use contention of the input / output control devices 20 and 22 is prevented between the central processing units 2 and 12. Fault detection apparatus 30 includes a channel device 3,13 input signal failure detector 30 ₁ by a signal input from the input-output control unit 20, 22, channel device failure detector 30 output signal by the output signal from 3,13 _{Consists of two} . Figure 2 is failure detector 30 for input signals of the fault detection device 30 ₁
It is a block diagram of. Input signal failure detector 30 ₁ mainly includes a first FIFO (First
-In First-out) memory 43, a write control circuit 40 for controlling a write operation to the first FIFO memory 43, and a first FIFO
The read control circuit 46 controls a read operation from the memory 43. The case where the input / output bus 4 is an act system and is operated in the collation mode will be described as an example. Due to the master-slave relationship of the central processing unit, the input / output bus 14 is in the standby mode and is in the verification mode. The inverted version of the act signal is the standby signal. The collation mode signal line 51 and the act signal line 52 are “1”. On the other hand, the collation mode signal line 61 is “1” while the act signal line 62 is “0”. When an input operation is started from the input / output control device 20 or 22 to the channel device 3 on the input / output bus 4, the input signal line 50 is enabled “1”. As a result, the write control circuit 40 starts operating. The signal on the input / output bus 4 is sent to the AND circuit 41 via the connection bus 53. The AND circuit 41 sends the data on the connection bus 53 to the first FIFO memory 43 because the act signal line 52 is "1". On the other hand, the AND circuit 42 does not send the data of the connection bus 63 to the first FIFO memory 43 because the condition is not satisfied because the act signal line 62 is “0”. The write control circuit 40 is a first FIFO memory
The output of the AND circuit 41 is written into 43 every clock of the input / output bus 4. The act signal line 52 is inverted by the inverter circuit 47 to become “0” and supplied to the AND circuit 44 and the read control circuit 46. Therefore, the condition of the AND circuit 44 is not satisfied, and the read control circuit 46 is not activated from the input / output bus 4. On the other hand, the signals on the input / output bus 14 are such that the act signal line 62 is disabled "0" and the collation mode signal line 61 is "1". Input / output operation from 22 is started,
Even if the input signal line 60 is enabled "1", the write control circuit 40
Is not invoked. The act signal line 62 is inverted by the inverter circuit 48 and supplied to the AND circuit 45 and the read control circuit 46. When the input signal line 60 is enabled, the read control circuit 46 starts operating, and reads data from the first FIFO memory 43 to the internal bus 49 every clock of the input / output bus 14. The read signal is sent to AND circuits 44 and 45 via internal bus 49. The condition of the AND circuit 44 is not satisfied, the condition of the AND circuit 45 is satisfied, and the data on the internal bus 49 is
The data is sent to the input / output bus 14 via the input / output bus 64. This means that the input signal of the input / output bus 4 is transmitted via the first FIFO memory 43
14 means sent. Buses 53, 63, 49, 5
4, 64 includes a data line and a control line. Also in the case where the input / output bus 14 is act and the input / output bus 4 is standby and in the verification mode, the same operation is performed in a state where the input / output bus 4 and the input / output bus 14 are exchanged. Hereinafter, a schematic operation will be described. The write control circuit 40 is activated from the input / output bus 14 and the signals on the input / output bus 14
Is written to the first FIFO memory 43 through the AND circuit 42. The read control circuit 46 is not activated from the input / output bus 14, and the write control circuit 40 is not activated from the input / output bus 4.
The read control circuit 46 is activated from the input / output bus 4 and outputs the first FI
The contents of the FO memory 43 are read out to the internal bus 49. The data on the internal bus 49 is sent out to the input / output bus 4 via the connection bus 54 by the AND circuit 44. This means that the input signal of the input / output bus 14 is sent to the input / output bus 14 via the FIFO memory 43. When the first FIFO memory 43 is full, the write control circuit 40 sends an input full signal to the signal line 31 to notify the central processing units 2 and 12. This means that the input operation of the standby-side channel device was not performed even though the input operation of the act-side channel device was performed and the first FIFO memory 43 became full. Either the processing system (storage device, central processing unit, channel device, input / output bus,..., Etc.) or the standby side processing system has failed. Therefore, in a normal state, the delay (shift) of the standby-side input / output bus with respect to the act-side input / output bus needs to be within (input / output bus clock time) × (capacity of the first FIFO memory 43). In other words, it means that the delay (shift) is allowed within (input / output bus clock time) × (capacity of the first FIFO memory 43). Further, the input signal failure detector 30 ₁ not to operate except when collation mode. Figure 3 is an output signal failure detector 30 of the failure detector 30 ₂
It is a block diagram of. Output signal failure detector 30 ₂ mainly, the second FIFO memory 7
1, a write control circuit 70 for controlling the write operation, a read control circuit 72 for controlling the read operation, a third FIFO memory 81, and a write control circuit 80 for controlling the write operation.
It comprises a read control circuit 82 for controlling the read operation, and a collation circuit 90 for collating data in the second FIFO memory 71 and the third FIFO memory 81. An example in which the input / output bus 4 is an act system and is operated in the collation mode with the input / output bus 14 is described. When an output operation is started from the channel device 3 to the input / output bus 4 to the input / output control device 20 or 22, the output signal line 55 is enabled “1”. Since the collation mode signal line 51 is also "1", the write control circuit 70 starts operating. The write control circuit 70 transmits the signal on the input / output bus 4 to the second FIFO
The data is written to the memory 71 every clock of the input / output bus 4. The write control circuit 70 sets the signal line 74 to “0” when at least one data exists in the second FIFO memory 71. Signal line 74 is an inverter circuit
The signal is inverted by 73 and supplied to the AND circuit 91. On the other hand, when an output signal is sent from the channel device 13 to the input / output bus 14 for the verification mode, the output signal line 65 is enabled. Since the collation mode signal line 61 is also "1", the write control circuit 80 starts operating. The write control circuit 80 writes the signal on the input / output bus 14 to the third FIFO memory 81 via the connection bus 85 every clock of the input / output bus 14. The write control circuit 80 sets the signal line 84 to "0" when there is at least one data in the third FIFO memory 81. The signal on the signal line 84 is inverted by the inverter circuit 83 and sent to the AND circuit 91. When the write control circuits 70 and 80 store data in the second and third FIFO memories 71 and 81, respectively, the condition of the AND circuit 91 is satisfied. The signal line 95 is enabled by the AND circuit 91, and the read control circuits 72 and 82 start operating. The read control circuit 72 reads data from the second FIFO memory 71 and sends it to the matching circuit 90 via the internal bus 76, and the read control circuit 82 reads data from the third FIFO memory 81 and connects the internal bus 86 The signal is supplied to the collating circuit 90 via the control unit. The matching circuit 90 is connected to the internal bus 76
And outputs the data 86 and outputs "0" to the signal line 94 if they match, and outputs "1" to the signal line 94 if they do not match. The signal on the signal line 94 is sent to the AND circuit 93. The other input of the AND circuit 93 is a signal of the matching mode signal lines 51 and 61. Therefore, when the matching circuit 90 detects the mismatch, the condition of the AND circuit 93 is satisfied, and the mismatch signal “1” is transmitted to the signal line 32. This mismatch signal "1" is sent to the central processing units 2 and 12 to notify a fault. The operations of the read control circuits 72 and 82 are the second and third operations.
Automatically until the FIFO memories 71 and 81 are empty. This means that the output data of the input / output bus 4 and the input / output bus 14 are collated by the fault detection device 30, and the result is reported to the central processing units 2 and 12. The write control circuit 70 enables the signal line 77 when the second FIFO memory 71 becomes full. This full signal is sent to the OR circuit 92. The write control circuit 80 enables the signal line 87 when the third FIFO memory 81 is full. This full signal is an OR circuit
Sent to 92. When the OR circuit 92 receives at least one full signal, it sends a failure detection signal to the signal line 33 to notify the central processing units 2 and 12. This means that one of the input / output buses 4 or 14 performed an output operation but the other did not perform an output operation, and an act-based processing system (storage device, central processing unit,
Either a channel device, an input / output bus,...) Or a standby processing system is faulty. Therefore, the delay (shift) of the standby system input / output bus with respect to the act system input / output bus is normal within (input / output bus clock time × FIFO memory capacity). In other words, it means that a deviation up to (input / output bus clock time × FIFO memory capacity) is allowed. Further, the output signal failure detector 30 ₂ does not operate except when collation mode. [Effects of the Invention] As described above, according to the present invention, the act system writes input data from the input / output control device to the FIFO memory, and the standby system reads from the FIFO memory, and monitors the accumulation of data in the FIFO memory. In addition, the data output by the channel device of each system is written into a FIFO memory provided for each other system, the data is collated, and the stagnation of data in each FIFO memory is monitored, and the data stored in each FIFO memory is monitored. Of the central processing unit and the other central processing unit at the clock level, it is possible to verify the processing results without having to synchronize the central processing unit with the other central processing unit at the clock level. In the control device, it is sufficient to return the operation result only to the activated side without being conscious of the collation mode of the central processing unit, and the circuit can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an information processing system provided with an embodiment of a failure detection device according to the present invention, and FIG. 2 is a failure detection for an input signal of the failure detection device 30 in FIG. block diagram of the parts 30 _1, Figure 3 is a block diagram of an output signal failure detector 30 ₂ of the fault detection device 30 in FIG. 1, FIG. 4 is a block diagram of a conventional example of duplicated information processing system . 1,11 storage device, 2,12 central processing unit, 3,13 channel device, 4,14 input / output bus, 20,22 input / output control device, 21,23 input Output device, 31, 32, 33, 77, 87, 94, 95
... signal lines, 40, 70, 80 ... write control circuits, 41, 42, 44, 45,
91, 93 ... AND circuit, 43 ... first FIFO memory, 71 ...
... Second FIFO memory, 81 ... Third FIFO memory, 46,72,
82 …… Read control circuit, 47,48,73,83 …… Inverter, 49,
76,86 …… Internal bus, 50,60 …… Input signal line, 51,61 ……
Verification mode signal line, 52, 62 ... Act signal line, 53, 54, 63,
64,75,85… Connection bus, 55,65… Output signal line, 90 ……
Matching circuit, 92 OR circuit.

Claims (1)

(57) [Claims] In an information processing system in which a storage device, a central processing unit, and a channel device are duplicated and are connected to a plurality of input / output buses, a first FIFO memory and an input / output bus for each of the duplicated channel devices are provided. A first connection bus for writing and a second connection bus for reading connecting the first FIFO memory and the first FIFO memory; and an output from the input / output control device for an act channel device operating in the collation mode. When the input signal is input,
First writing means for writing the signal to the first FIFO memory via the first connection bus and outputting a signal indicating the fullness when the first FIFO memory is full; By inputting a signal from the control device, the standby channel device operating in the collation mode puts its input / output bus into a data input state, thereby reading data from the first FIFO memory and setting the second connection bus. First read means for outputting to a standby system input / output bus via a second FIFO memory; a third connection bus connecting the act system input / output bus to the second FIFO memory; When a signal is output from the operating channel device of the act system to the input / output control device, the signal is output to the input / output control device when the second FIFO memory is full via the third connection bus. Second writer Dan and the third FIFO
A fourth connection bus for connecting a memory, a standby input / output bus and a third FIFO memory, and a fourth output bus for outputting a signal output from the standby channel device operating in the matching mode to the input / output bus to a fourth connection bus. A third writing means for writing to the third FIFO memory via the connection bus, and outputting a signal indicating the fullness when the third FIFO memory is full; A second read means for simultaneously reading data; a signal indicating whether the output data of the second FIFO memory output by the second read means and the output data output from the third FIFO memory are matched or mismatched. A failure detection device having a collation means for outputting a message.