JPS62140153A - Duplicated data processor - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a system caused by a double fault by writing the same data to both working and spare systems and comparing the data read out of both systems with each other with a reading request given from a CPU of the working system. CONSTITUTION:The contents of a memory device 4 are read out in response to a reading request given from a CPU 2 of own working system 1. At the same time, the contents of a memory device 4' of another spare system 1' are also read out via the double interface circuits 5 and 5'. Here the same data is written to the same address of the system 1' via the circuits 5 and 5'. These data read out in synchronism with each other are compared with each other by the CPU 2. When no coincidence is obtained from the comparison, the error information is produced. As a result, the coincidence is secured be tween the contents of both memories. The generation of the breakdown of a system caused by a double fault is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a redundant standby type data processing apparatus in which a central processing unit, a memory device, etc. are duplicated.

[1 Already Required] The present invention provides, in a duplex data processing device that stores the same data in a current memory and a spare memory, the data in the spare memory is destroyed by verifying that the data stored in the memories match. This can be detected in advance before switching to the standby system.

[Conventional technology]

In conventional duplex data processing devices, when data is written to the memory device of the own system, the same data is written to the memory device of the other system, thereby smoothly switching systems in the event of a failure.

[Problem that the invention seeks to solve]

In such conventional examples, when reading instructions or data, the data is read only from the memory device of the own system, so even if a failure occurs in the memory device of the other system and the data is destroyed,
There was no means to detect it, and the fault would be detected only after the system was switched and shut down, resulting in the system going down due to double faults.

The present invention aims to eliminate such drawbacks, and aims to provide a duplex data processing device that can detect failure of data stored in two memories before switching systems.

[Means for solving problems]

The present invention writes the same data to a first memory included in the active system, a second memory included in the backup system, and areas with corresponding addresses in the first memory and second memory. The duplex data processing device is characterized by comprising a comparing means for comparing data read from correspondingly addressed areas of the first memory and the second memory.

[Effect]

The same data is written to the active system and the backup system. However, the written data does not always match due to noise and other factors.

The present invention detects this mismatch by sending a memory read request from the active central processing unit to the active and backup memories, and comparing the read data from these two memories in a comparison circuit. , error information is generated when there is a mismatch. This ensures that the contents of the two memories match.

Setting of this mode is based on instructions from the central processing unit.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing the configuration of a device according to an embodiment of the present invention, which includes a local system 1 and a foreign system 1'.
In the own system 1, a central processing unit 2 and an input/output control unit 3 are connected to a memory device 4 and a duplex interface circuit 5 via a bus 6. Furthermore, the other system 1' has the same configuration as the own system 1. Further, the own system 1 and the other system 1' are connected via a bus 7 by duplex interface circuits 5 and 5'. FIG. 2 is a block diagram showing the configuration of the duplex interface circuit 5 of this embodiment, and shows the configuration of the bus 6.
and the interface space includes control lines 60 and 70, data lines 61 and 71, and address line 62, respectively.
and 72. The duplex interface circuit 5 includes an access sending circuit 8 that accepts access from the bus 6 and sends it to the lotus 7, an access sending circuit 9 that receives access from the lotus 7 and sends it to the lotus 7,
A comparison circuit 10 is provided to compare data read from the bus 6 and data read from the bus 7. The access sending circuit 8 that sends out accesses to the bus 7 includes a control circuit 81 , and the access sending out path 9 that sends out accesses to the bus 6 includes a control circuit 91 .

Next, the operation of the present invention will be explained based on FIGS. 3 to 5. The duplex system 1 has three operating modes: asynchronous mode, copy mode, and synchronous mode. First, in the asynchronous mode, an access path is formed from the central control unit 2 of the own system to the measuring device 4' of the other system, as shown by the broken line in FIG.

Both reading and writing are possible using this path.

When the central processing unit 2 accesses the memory device 4 of its own system in the asynchronous mode, the redundant interface circuit 5 does not operate. Next, in the copy mode, as shown in FIG. 4, the read data is read from the own system's memory device 4 when reading, and the read data is read from both the own system's memory device 4 and the other system's memory device W4' when writing. The same data is written to the same location. That is, the bus through which data passes during reading is the central processing unit 2 bus 6 memory device 4 bus 6 central processing unit 2, whereas the bus during writing is the central processing unit 2 bus 6 interface bus access sending circuit 9' bus 6' becomes a memory device 4'. Next, in the synchronous mode, the bus at the time of writing is the same as that shown in FIG. 4, and the bus at the time of reading is as shown in FIG. This is a comparison circuit 10. In this mode, a memory read request from the central processing unit 2 is sent to the memory device 4 of the own system and the sending device 4' of the other system.
The data read from the memory device 4 of the own system and the data read from the memory device 4' of the other system are compared in the comparison circuit 10, and if they do not match, error information is sent to the memory access destination. The contents of the memory device 4 of the own system at the address and the contents of the sending device 4' of the other system are compared every time.

Now, the transition between these modes is asynchronous mode at startup, and the memory contents of the local system and other systems are different, but before changing to synchronous mode, change the memory contents of the local system and other systems by switching to copy mode. can be matched. That is, a memory copy can be performed by reading the memory from address O of the own system and sequentially writing the read data. Next, in the synchronous mode, read data is compared at the time of reading to ensure that the contents of the own system memory and the other system memory match. The above three modes are controlled by the control signal v in the bus 6 from the central processing unit 2.
It enters the control circuit 81 of the duplex interface circuit 5 via A60, where the access bus is determined.

In principle, the comparison means can be activated at any time. It can be started at regular intervals, or it can be started before or after some processing.

〔Effect of the invention〕

As explained above, the present invention has the effect of reducing the risk of system down due to double failure, since the redundant standby backup type data processing system collates the data of the local memory and the other system memory in the synchronous mode. .

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the duplex interface circuit shown in FIG. 1. 3 to 5 are explanatory diagrams showing the operation of the apparatus according to the embodiment of the present invention. 1... Own system, 1'... Other system, 2.
2'... Central control device, 3.3'... Human output control device, 4.4'... Memory device, 5.5'... Duplex ink face circuit, 6.6'... Bus, 7... Interface path, 8.8', 9.9'... Access output path, 10.10'... Comparison circuit, 6o, 7o.
...Control line, 61.71...Data line, 62.72.
...Address line, 81.91...Control circuit. Patent distributor: NEC Co., Ltd. Agent: Naotaka Ide, patent attorney Structure of the embodiment Fig. 1 Fig. 2 Explanation of operation Fig. 3 Explanation of operation Fig. 4

Claims (1)

[Claims] (1) A first memory included in the active system, a second memory included in the backup system, and means for writing the same data into areas with corresponding addresses in the first memory and second memory. A duplex data processing device comprising: a comparison means for comparing data read from correspondingly addressed areas of the first memory and the second memory. .