JPH0683720A - Data backup type computer system - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU by shortening the data backup operation time of the CPU at the occurance of service interruption and to use an inexpensive power supply using a capacitor with low capacity in respect to a data backup type computer system for transferring important data being processed immediately before the generation of service interruption to a memory so as to hold data even in a service-interrupted state. CONSTITUTION:A backup memory device 6A is constituted of a memory part 7 for storing data in a main memory device 3 for a prescribed time from the power OFF, a reference memory part 8 having the same writing address as that of the memory part 7a and a backup data comparing/checking part 10 for comparing data written in the memory part 8 with data written in the memory part 7 to check backup data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data backup type computer system for transferring important data being processed to a memory immediately before a power failure and retaining the data even in a power failure state.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 5, a central processing unit (CPU) 1, an I / O unit 2 and a main memory unit 3 are connected to each other via a system bus 4 and a power supply unit is also provided. In a computer system which is powered by 5 and operates, a backup memory device (for example, an EEPROM) 6 is connected to the system bus 4 so as not to lose important data being processed immediately before a power failure. The data being processed immediately before the power failure and the data in the main memory device 3 are transferred to the memory section of the backup memory device 6, and the data is retained even in the power failure state.

By the way, the power supply unit 5 is constructed as shown in FIG.
Is made. In FIG. 6, 5a is a primary side input
(AC input or DC input) S₁Secondary side output (DC output
Power) S ₂AC / DC (or
Or DC / DC) converter, 5b is this AC / DC converter
Secondary side output S of 5a₂Secondary output abnormality that detects abnormalities in
The detector 5c is the primary side input S of the AC / DC converter 5a.₁
Input abnormality detecting section for detecting abnormalities in
Anomaly detection signal S from the output anomaly detector 5b_FourAnd primary
Abnormality detection signal S from the side input abnormality detection unit 5c₃Received
Blackout warning signal S_FivePower failure warning output section that outputs the data to CPU1
Is.

As shown in FIG. 7, when the primary side input abnormality detecting section 5c detects an abnormality in the primary side input S ₁ (falling of the input), the power source section 5 having such a configuration detects the primary side input abnormality. rise abnormality detection signal S ₃ from the parts 5c, the power failure alarm output unit 5 which has received the abnormality detection signal S ₃
d raises the power failure warning signal S ₅ and outputs it to the CPU 1. Then, the AC / DC converter 5a receives the primary side input S
Secondary side output S for a predetermined time T ₁ after ₁ falls
_A capacitor (not shown) capable of holding the output state of ₂ is provided.

Further, CPU 1 from the power supply unit 5 has received the power failure alarm signal S ₅ is the predetermined time T ₁ within which the output state of the secondary side output S ₂ of the power supply unit 5 is held, just before the power failure in the process data , All the data in the main memory device 3 is transferred to the backup memory device 6, and the data is held in the memory portion of the backup memory device 6 even in the power failure state.

[0006]

However, the general EEPR as the memory unit of the backup memory device 6 is used.
When OM is used, due to the specifications of the EEPROM memory,
For example, first, after writing the data for a writing time t _{1 of} about 170 ns and after waiting time t ₂ of about 10 ms, check the written data.
Since the write data is read to the CPU 1 over the read time t _{3 of} about 400 ms, as shown in FIG.
When the byte EEPROM is used, it takes about 81.9 s to write data to all addresses.

Therefore, the CPU 1 is occupied by the data backup operation for a long time of 81.9 s, which increases the load on the CPU 1 and
The predetermined time T ₁ for holding the output state of the secondary side output S ₂ of the power supply unit 5 shown in FIG. 7 must be set to 81.9 s or more, and it is necessary to equip an extremely large capacity capacitor,
This is a factor in increasing the cost required for the device.

The present invention was devised in view of the above problems, and can reduce the load on the CPU and reduce the load on the CPU by shortening the data backup operation time by the CPU when a power failure occurs. It is an object of the present invention to provide a data backup method in which an inexpensive power supply unit using a low-capacity capacitor can be used by shortening the holding time of the secondary output.

[0009]

FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, 1 is a CPU (central processing unit), 3 is a main memory device, 4 is these CPU 1, main memory device 3 , A system bus for connecting a backup memory device 6A, which will be described later, through the system bus 4
PU1, main memory device 3, backup memory device 6A
Are connected to form a computer system.

Then, in order to hold the data in the main memory device 3 (data being processed by the CPU 1) in the memory portion 7 of the backup memory device 6A within a required time after power-off, the backup memory device 6A In addition to the memory section 7 for data backup, a reference memory section 8 having the same write address as the write address to the memory section 7, and an address generation section for giving a common address to the memory section 7 and the reference memory section 8 Backup data comparison and checking the backup data by comparing the data written in the reference memory unit 8 with the data written in the memory unit 7.
The check unit 10 and the control unit 11 are provided.

The backup data comparing / checking unit 10 further includes a data comparing unit 10a for comparing the data written in the reference memory unit 8 with the data written in the memory unit 7, and the data comparing unit 10a. The backup data check unit 1 that checks the backup data from the comparison result and sends the check result to the CPU 1.
0b and 0b.

Further, the control unit 11 stores the data in the main memory device 3 in the memory unit 7 and the reference memory unit 8 when the power is cut off.
To the reference memory unit 8 and the data written to the memory unit 7 sequentially, and both data are compared by the backup data comparison / check unit 10 to check the backup data. Is something that is done.

[0013]

In the above-described data backup type computer system of the present invention, the data in the main memory device 3 is responsive to the address from the address generator 9 controlled by the controller 11 within a required time after the power is turned off. , Are simultaneously written to the memory unit 7 and the reference memory unit 8 in the backup memory device 6A at the same address.

After the writing is completed, the address generator 9 outputs a common address to the memory unit 7 and the reference memory unit 8 in response to a command from the control unit 11, and the data written in the reference memory unit 8 is written. And the data written in the memory unit 7 are sequentially read, and both data are compared by the data comparison unit 10a of the backup data comparison / check unit 10.

Thereafter, the backup data check unit 10b of the backup data comparison / check unit 10 checks the backup data from the comparison result of the data comparison unit 10a, and the check result is C
It is sent to PU1.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 2 is a block diagram showing the overall configuration of a data backup type computer system as an embodiment of the present invention. First, the overall configuration of the computer system of the present embodiment will be briefly described with reference to FIG. 2 as shown in FIG. The computer system of this embodiment is also constructed in substantially the same way as the conventional system shown in FIG.

That is, the CPU via the system bus 4
(Central processing unit) 1, I / O unit 2, main memory device 3, backup memory device 6A of this embodiment are connected to form a computer system, and power is supplied from a power supply unit 5 to this computer system. It is supposed to be. Here, the power supply unit 5 is configured in exactly the same manner as that shown in FIG. 6, and when an abnormality occurs in the power supply unit 5, the power failure warning signal S ₅ is transmitted from the power supply unit 5 as CP.
It is designed to be output to U1. CPU1 which receives the power failure alarm signal S ₅ from the power supply unit 5, so as not to lose important data just before the power failure, the backup memory device 6A
A backup command is output to the memory unit 6a and the data in the main memory device 3 is transferred to and held and stored in the memory unit 6a of the backup memory device 6A within a required time after the power is turned off.

Next, the configuration of the backup memory device 6A of this embodiment will be described with reference to FIG. 3. In FIG. 3, 7A is the main memory device 3 within a required time after the power is turned off.
An EEPROM (electrically erasable memory; memory unit) for holding / storing the data in the internal memory, and a memory unit, 8A are arranged in parallel with the EEPROM 7A and are mainly arranged at the same write address as the write address to the EEPROM 7A. A RAM (reference memory section) 9 for storing data in the memory device 3 is an address generating section for giving a common address to the EEPROM 7A and the RAM 8A via the address bus 17.

Data to the EEPROM 7A and the RAM 8A is sent to an address generator through a data bus 13 connected to the system bus 4 (see FIG. 2), a gate 12 controlled by a controller 11 described later, and a data bus 14. It is adapted to be written to a common address generated by 9. Reference numeral 10 denotes a backup data comparison / check unit for checking the backup data by comparing the data written in the RAM 8A with the data written in the EEPROM 7A. The backup data comparison / check unit 10 includes the address generation unit 9 And a data comparison unit 10a for receiving the data read from the EEPROM 7A and the RAM 8A in accordance with the common address generated by the data bus 15 and 16 and comparing the data with each other. The result is received via the response line 23, the backup data is checked, and the check result S ₇ is sent to the signal line 25.
The backup data check unit 10b is sent to the CPU 1 through the.

Further, 11 is an address generator 9, a gate 12 and an EEPROM via control lines 18 to 22, respectively.
7A, RAM 8A, and a backup data comparison / check unit 10, which controls the gate 12 and the address generation unit 9 when the power is turned off so that the data in the main memory device 3 can be stored in the EEPROM 7A and RA.
M8A writes at the same address at the same time, and when it receives a memory check command S ₆ from the CPU 1 via the signal line 24, it controls the address generation unit 9 and the backup data comparison / check unit 10 to write the data and the memory written in the RAM 8A. The data written in the unit 7 is sequentially read and both data are compared by the backup data comparing / checking unit 10 to check the backup data.

With the above configuration, when an abnormality occurs in the power supply unit 5, the power supply unit 5 outputs the power failure warning signal S ₅ to the CPU 1 in the same manner as the procedure described above with reference to FIGS. The CPU 1, which receives the power failure warning signal S ₅ , receives the processing data immediately before the power failure and the main memory device 3 within the predetermined time T ₁ during which the output state of the secondary side output S ₂ of the power supply unit 5 is maintained.
All data in the backup memory device 6A is transferred to the EEP of the backup memory device 6A.
A backup command is output so as to hold it in the ROM 7A.

At this time, in the backup memory device 6A of this embodiment, the data in the main memory device 3 is transferred from the address generator 9 controlled by the controller 11 within the required time T ₁ after the power is turned off. Depending on the common address,
Moreover, the data is simultaneously written in the EEPROM 7A and the RAM 8A at the same address via the gate 12 controlled by the control unit 11.

Then, after the writing is completed, the control unit 11 controls the address generation unit 9 to read the EEPROM 7A and the RAM 8A.
The common address is automatically changed and output to RAM8
The data written in A and the data written in the EEPROM 7A are sequentially read, both data are input to the backup data comparison / check unit 10, and these data are compared by the data comparison unit 10a.

After this, the comparison result of the data comparison unit 10a is transferred to the backup data check unit 1 via the response line 23.
0b, the comparison result is checked and held by the backup data check unit 10b, and the control unit 11b
However, when receiving the memory check command S ₆ from the CPU 1, the check result S ₇ is sent to the CPU via the signal line 25.
Send to 1.

As described above, according to the data backup type computer system of this embodiment, the EEPROM 7A
Checking the data stored in the backup memory device 6A without reading to the CPU 1
This is performed by comparing with the data written in the same address of RAM 8A, and the read data check processing operation can be performed as shown in FIG.

That is, there is no need to perform writing / reading for each address and checking data by the CPU 1 as in the conventional case shown in FIG. 8. In this embodiment, as shown in FIG. 4, writing and reading are performed. Can be done collectively,
When using 8k / byte EEPROM, the time required to write data to all addresses is only 14.6m.
s, which is significantly shorter than the conventional 81.9s.

In the conventional system, the above-mentioned 8
Although the CPU 1 was occupied by the data backup operation for a long time of 1.9 s, in the system of this embodiment, the data check is performed by the backup memory device 6.
Since it is carried out in A, the time occupied by the data backup operation is a backup command of several μs to the backup memory device 6A and the write time 1.
The total time of 4 ms and the number of backup completion interrupt processing μs is about 2 ms.

Therefore, the data backup operation time by the CPU 1 at the time of power failure can be greatly shortened, and C
The load on the PU 1 can be greatly reduced, the holding time T ₁ of the secondary side output of the power supply unit 5 can be shortened, and an inexpensive power supply unit using a low-capacity capacitor can be used.

[0029]

As described above in detail, according to the data backup type computer system of the present invention, the data in the main memory device is controlled by the address generation unit controlled by the control unit within the required time after the power is turned off. According to the address from, after writing at the same address to the memory section and the reference memory section in the backup memory device at the same time,
The address generation unit outputs a common address to the memory unit and the reference memory unit in response to a command from the control unit, and the data written in the reference memory unit and the data written in the memory unit are sequentially read out. Since the data is configured to be compared / checked by the backup data comparison / check unit, the data backup operation time by the CPU in the event of a power failure can be shortened, the load on the CPU can be reduced, and the secondary side output of the power supply unit can be reduced. The holding time can be shortened, an inexpensive power supply unit using a low-capacity capacitor can be used, and the cost required for the device can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing the overall configuration of a data backup type computer system as an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a backup memory device in this embodiment.

FIG. 4 is a diagram for explaining a time required for checking backup data in the system of the present embodiment.

FIG. 5 is a block diagram showing an overall configuration of a conventional data backup type computer system.

FIG. 6 is a block diagram showing a general configuration of a power supply unit.

FIG. 7 is a timing chart for explaining general operation characteristics of a power supply unit.

FIG. 8 is a diagram for explaining a time required to check backup data in a conventional system.

[Explanation of symbols]

1 CPU (Central Processing Unit) 2 I / O Unit 3 Main Memory Device 4 System Bus 5 Power Supply Unit 6A Backup Memory Device 7 Memory Unit 7A EEPROM (Electrically Erasable Memory, Memory Unit) 8 Reference Memory Unit 8A RAM 9 Address generation unit 10 Backup data comparison / check unit 11 Control unit 12 Gate 13 to 16 data bus 17 Address bus 18 to 22 Control line 23 Response line 24, 25 Signal line

Claims (5)

[Claims] 1. A computer system in which a central processing unit (1), a main memory unit (3), and a backup memory unit (6A) are connected via a system bus (4) within a required time after power-off. In order to hold the data in the main memory device (3) in the memory part (7) of the backup memory device (6A), the backup memory device (6A) uses the memory part (7) for data backup. In addition to the above, a reference memory unit (8) having the same write address as the write address to the memory unit (7) is provided, and the data written in the reference memory unit (8) and the memory unit (7) are provided.
A data backup type computer system comprising a backup data comparing / checking unit (10) for checking backup data by comparing with the data written in. 2. The backup memory device (6A) comprises:
In addition to the memory unit (7), the reference memory unit (8) and the backup data comparison / check unit (10), a common address is given to the memory unit (7) and the reference memory unit (8). The data backup type computer system according to claim 1, characterized in that the computer system comprises an address generator (9). 3. A data comparison unit (10) in which the backup data comparison / check unit (10) compares the data written in the reference memory unit (8) with the data written in the memory unit (7). 10a) and the data comparison unit (10a)
2. The data backup computer system according to claim 1, further comprising a backup data check unit (10b) for checking the backup data based on the comparison result in a). 4. The memory unit (7) in the backup memory device (6A) is composed of an electrically erasable memory, and the reference memory unit (8) in the backup memory device (6A) is a RAM. The data backup computer system according to claim 1, wherein the data backup computer system comprises: 5. The data in the main memory device (3) when the power is turned off is stored in the memory part (7) and the reference memory part (8).
And the data written in the reference memory unit (8) and the memory unit (7) at the same time.
The backup memory device (6A) is provided with a control unit (11) for sequentially reading the data written in the backup data and comparing both data with the backup data comparison / check unit (10) to check the backup data. The data backup type computer system according to claim 1, wherein