JPH06110859A - Duplex system state confirming circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a duplex system and to reduce the load of a CPU for improvement of the system processing ability by grasping quickly the state changes of other systems to prevent the malfunction of system. CONSTITUTION:The circuit is provided with a CPU 1 which controls its own system, a buffer 3 which stores the state of its own system recognized by the CPU 1, a buffer 5 which stores the state of its own system pointed by the opposite party system, a comparator 7 which compares the pointed state of its own system stored in the buffer 5 with the state of its own system stored in the buffer 3, an interruption generating means 7 which produces an interruption to the CPU 1 when the discordance is confirmed by the comparator 7 between both states of its own system, and a means which reads the pointed state outof the buffer 5 and stores the state in the buffer 3 when an interruption is produced to the CPU 1 by the means 7. In such a configuration, the malfunction of a duplex system can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention compares the state recognized by the own system and the state of the own system instructed by the partner system in a duplex system having the own system and the partner system. The present invention relates to a duplicated system state recognition circuit that improves reliability and reduces the load on the CPU to improve the processing capacity of the system.

[0002]

2. Description of the Related Art A duplex system is used to improve the reliability and the processing capacity of a computer system, a plant and the like.

The operation of monitoring the duplex status of the duplex system will be described with reference to the flowchart of FIG.

First, a switching device is installed between the own system and the partner system, and various processes of the own system are executed for a certain period of time (depending on the system specifications) (step 200). After the elapse of a certain time, the switching device currently checks the status of the own system and the partner system by a program that monitors the status of the own system on the online side (step 210). If the status is changed to, for example, a slave by checking the status, a process suitable for the slave is executed in the own system and step 2 is executed.
00, and if there is no change in state, the process returns to step 200 (steps 220 to 230).

While the above operation is repeated, the state of the redundant system is periodically monitored by the switching device.
It was not easy to recognize the change of state quickly.

[0006]

However, in the conventional duplex system, the status of the own system, which is currently on-line side, is periodically monitored by the switching device at regular intervals, so that the own system performs another process. If the status changes during the execution, the processing of the relevant system malfunctions until the next monitoring, resulting in a decrease in the reliability of the system.

Further, there is a problem that the load of the CPU is increased by the operation of the program for monitoring the change of the state, and the processing capacity of the system is lowered.

The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to quickly grasp the change in the state of the partner system and prevent the malfunction of the system. Improves reliability and CP
It is an object of the present invention to provide a dual system state recognition circuit that reduces the load on U and improves the processing capacity of the system.

[0009]

In order to achieve the above object, the present invention provides a CPU for controlling its own system, an own system state storing means for storing the state of the own system recognized by this CPU, and a partner. An instruction state storage means for storing the state of the own system instructed by the system, the state of the instructed own system stored in the indicated state storage means and the own system stored in the own system state storage means And a comparator for comparing the state with the state of the own system stored in the own system state storage means by this comparator does not match the instructed own system state stored in the instruction state storage means. Interrupt generating means for generating an interrupt in the CPU, and when the interrupt generating means generates an interrupt in the CPU, the instructed state stored in the instructed state storage means is read out and stored in the own system state storage means. And summarized in that with the means.

[0010]

According to the above-described structure, the state of the own system instructed by the partner system stored in the instructed state storage means by the comparator and the state of the own system stored in the own system state storage means are stored. Compare. By this comparison, when the state of the self system stored in the self system state storage means does not match the state of the self system instructed by the partner system stored in the instruction state storage means, an interrupt is generated in the CPU. Then, when an interrupt occurs in the CPU due to this interrupt, the state instructed by the partner system stored in the instructed state storage means is read out and stored in the own system state storage means, so that a malfunction of the system is prevented, The reliability of the system can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the control of an embodiment of the duplex system state recognition circuit of the present invention.

The redundant system state recognition circuit is a CP
The U1, the buffer 3, the buffer 5, and the comparator 7 are provided to quickly monitor the state of the own system recognized by the CPU 1 and the state instructed by the partner system.

The CPU 1 controls the entire system, is connected to the buffer 3 and the buffer 5 via the data bus 9, and is connected to the buffer 5 via the read control line 11 from the RD (read) terminal. Buffer 5
The state instructed by the partner system stored in the predetermined address of is read out via the data buffer 9. Also, C
The PU 1 writes the state of its own system, which is recognized, at a predetermined address of the buffer 3 via the write line 13 connected to the buffer 3 from the WR (write) terminal.

In the buffer 3, the CPU 1 stores, for example, an online or slave own system state at a predetermined address. The buffer 5 stores a state instructed by its own system and a partner system (not shown) in the duplex system at a predetermined address via the state instruction line 15.

The comparator 7 indicates the state recognized by its own system, which is stored at a predetermined address of the buffer 3, by the state recognition line 1.
The status indicating line 1 indicates the status designated by the partner system, which is inputted via 7 and stored at a predetermined address of the buffer 5.
The state recognized by the own system input via 5 and the state instructed by the partner system are compared. If they do not match as a result of comparison, the comparator 7 causes the interrupt line 19 connected to the INT (interrupt) terminal of the CPU 1 to be at a high level, and causes the CPU 1 to generate an interrupt.

The comparator 7 will be described with reference to the block diagram of FIG.

The comparator 7 is composed of a comparison LSI, and is provided with a buffer 5 and a status indication line 15 from the Q ₀ terminal and the Q ₁ terminal to the Q _n terminal.
It includes P ₀ terminal, from P ₁ terminal to P _n terminals by state recognition line 17 between. From the Q ₀ terminal to the Q _n terminal of the status indicating line 15 and the P ₀ terminal, P _{1 of the} status recognition line 17
There is a one-to-one correspondence from the terminals to the P _n terminals, and when the status detection terminals, for example, P ₃ and P ₄ and Q ₃ and Q ₄ have different values, the interrupt line 19 is set to the high level. Then, the INT terminal of the CPU 1 is set to a high level to generate an interrupt.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. 3 (a) and the flowchart of FIG. 3 (b).

First, after the system is activated, the CPU 1 writes the state recognized by the system, for example, online to the write control line 13 at a high level to a predetermined address of the buffer 3 via the data bus 9. The recognized state written in the predetermined address of the buffer 3 is output to the comparator 7 and the partner system via the state recognition line 17. On the other hand, the status of the own system designated by the partner system via the status designation line 15 is stored at a predetermined address of the buffer 5. The instructed state of the own system stored at a predetermined address of the buffer 5 is output to the comparator 7 via the state instruction line 15. The comparator 7 compares the state of the own system, which is instructed by the partner system, which is input via the state instruction line 15, with the recognized state of the own system, which is input through the state recognition line 17 (step 100).

By comparison, if the state of the own system instructed by the partner system matches the state of the own system recognized by the own system, the INT terminal of the CPU 1 shown in FIG. Then, in the case of disagreement, the comparator 7 generates an interrupt and the I of the CPU 1 shown in FIG.
NT terminal goes high (steps 110-12)
0).

After the occurrence of the interrupt, the CPU 1 sets the read control line 11 to the high level and reads the state of the own system, which is stored at a predetermined address of the buffer 5 and instructed by the other system, through the data line 9. The read status of the own system is stored in a predetermined address of the buffer 3 and output to the comparator 7 and the partner system via the status recognition line 17. When the recognized self-system state stored in the predetermined address of the buffer 3 is input to the comparator 7, it is inputted via the state indication line 15 and the designated self-system state and the state recognition line 17 are inputted. The recognized state that is input as is matched. If they match, the interrupt ends and the CPU1 IN shown in FIG.
The T terminal goes low and the process returns to step 100 (step 130).

As a result, if the state instructed by the partner system and the state recognized by the own system do not match, the CPU
Since the interrupt is generated at 1, the malfunction of the own system does not occur.

Further, since the program for monitoring the redundant system is not required, the load on the CPU 1 can be reduced.

[0025]

As described above, according to the present invention, the state recognized by the own system is compared with the state instructed by the partner system, and when the states do not match, the set state is set. It is possible to improve the system reliability by promptly grasping the change in the state of the partner system and preventing the malfunction of the system, and reduce the load on the CPU to realize the improvement of the processing capability of the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing control of a redundant system state recognition circuit of the present invention.

FIG. 2 is a block diagram showing a comparator.

FIG. 3 is a time chart showing the operation of the present invention.

FIG. 4 is a flowchart showing the operation of the present invention.

[Explanation of symbols]

 1 CPU 3, 5 Buffer 7 Comparator 15 Status indication line 17 Status recognition line 19 Interrupt line

Claims (1)

[Claims] 1. A CPU controlling an own system, an own system state storing means for storing a state of the own system recognized by the CPU, and an instruction state memory for storing a state of the own system instructed by a partner system. Means and a comparator for comparing the instructed self-system state stored in the instructed state storage means with the self-system state stored in the self-system state storage means, and the comparator by the comparator. Interrupt generating means for generating an interrupt to the CPU when the state of the own system stored in the system state storing means does not match the instructed state of the own system stored in the instruction state storing means; And a means for reading out an instructed state stored in the instructed state storage means and storing it in the self-system state storage means when an interrupt occurs in the CPU by the means. State recognition circuit.