JPS61248141A - Fifo self-diagnosing device - Google Patents

Abstract

PURPOSE:To make it possible to make operation check by the operation of only one CPU in a multi-CPU system suing an FIFO by providing newly a bus interface section and a spurious control signal generating section. CONSTITUTION:By outputting data to be transferred to a CPU to DBUS 1 and generating a WR signal to FIFO 3, data on the DBUS 1 are stored in FIFO 3. The data bus of the CPU 2 and controlling signal are separated from FIFO in a bus interface section 5 and made to high impedance state. A spurious READ signal TR is generated in FIFO from a spurious control signal generating section 6 provided in the CPU 1, and data stored in FIFO are outputted to a DBUS 3. A spurious WRITE signal TW is generated from the spurious control signal generating section to FIFO 4, and data on the DBUS 3 are stored in FIFO 4. An RL signal is generated to FIFO 4 and the operation check of FIFO is completed by comparing read data by the CPU 1 with the data outputted first from the CPU 1 to FIFO 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multi-CPU system equipped with a transmitting/receiving FIFO for the purpose of exchanging data between CPUs.
This invention relates to a self-diagnosis device.

Conventional technology In recent years, as computer systems have become more sophisticated and complex, multi-CPU systems with multiple CPUs are increasing.In these systems, FIFO is used to exchange data between CPUs. There are things that are.

Hereinafter, a conventional method of transmitting and receiving data between CPUs in a multi-CPU system using a FIFO and checking the operation of the FIFO will be explained with reference to the drawings.

FIG. 4 is a block diagram of a conventional system in which data is exchanged between two CPUs using a transmitting/receiving FIFO.

1' and 2' are CPU, CPU ashi, and K, respectively.
Generate READ signal for FIFOK1. , PIFO
After reading the stored data, a WRITE signal is generated to the FIFO, and the data is written to the FIFO. 3' is from CPU i' to CPU
FIFO for transferring data to CPU 2'.
WRITE signal (WR) from 1' and CPU 2'
It is controlled by the READ signal (R2) from GC. 4
' is PIF04' for transferring data from CPU2' to CPU1', and WRI from CPU2'
It is controlled by the TE credit (W2) and the READ signal (RL) from CPU 1'. DBUS1 is a data bus that connects these two FIFOs and CPtJ1', and DBUS2 is a data bus that connects the FIFO and CPU2'.

The operation of the data exchange system between multiple CPUs using the transmitting/receiving FIFO configured as described above will be explained below.

First, to explain the case where data is transferred from CPU 1' to CPU 2', CP tJ 1' is transferred from DBU
Output the data to be transferred onto S1, and
' generates a WRITE signal (WR). As a result, the data on DBUS1 is stored in PI FO3'. Next, the data stored in FIFO3' is transferred to the CPU
READ signal (R
2) Output from K to DBtJ32 and send it to CPU2
′ takes in K from CPU 1′ to CPU 2′
Data transfer will take place.

Similarly, in the case of data transfer from CPU 2' to CPU 1', the data output by CPU p' is stored in PIFO 4' via DBUS2 via the WRITE signal (W2) from CPU 2' to FIFO 4'. Then, the CPU 1' sends the READ signal (RL) to the FIFO 4' through the DBUS 1.
It is taken into U1'.

Problems to be Solved by the Invention However, in the above configuration, the following method is required to check the operation of the FIFO.

First, data output from CPU 1' is stored in FIFO 3', and this data is sent to FIFO 3' of CPU 2'.
The data is once input to the CPU 2' by the EAD operation. The operation of the FIFO 3' can be checked by comparing this input data with the data output by the CPU 1'. Similarly, the operation check of PIF04' is performed by CPU 2.
CPU 1' writes the data written to FIFO4' by '.
By the READ operation for FIFO4', the CPU
1' and compare the data.

Alternatively, the data output from CPU1' can be sent to CPU2'.
After importing through FIFO3', it is transferred directly to the FIFO
If it is returned to CPU 1' through O4', CPU 1
By comparing the output data to FIFO3' and the input data from PIFO4' on the side, KFIFO3
' operation check becomes possible.

However, in any case, CPU 1' and CPU 2'
Both READ and WRITE operations are required,
In other words, the CPU 1' is used to check the operation of the FIFO.

Software for both CPU 2' is required, and of course a portion of memory for storing this software must exist in both CPU 1' and CPU 2'.

Furthermore, if CPU 1' and CPU 2' are separated into two boards, the FI
It becomes impossible to check the operation of the FO.

As manufacturing and inspection processes become more streamlined, the above-mentioned operation check methods are extremely inefficient, and there has been a desire to develop a simple operation check method.

In view of the above-mentioned problems, the present invention provides a FIFO self-diagnosis device that performs a FIFO operation check, which is normally realized only by the operation of two CPUs, by using the READ operation and WFLITE operation of one CPU. be.

Means for Solving the Problems In order to solve the above problems, the FIFO self-diagnosis device of the present invention has the following features:
A bus interface unit for electrically separating the RITE signal and the data bus from the FIFO, and the PIF
This configuration includes a pseudo control signal generating section that generates a control signal from the CPU in place of the 0READ-WRITE signal for OK.

The PIFO of the second CPU is controlled by the working path interface section.
The READ@WRITE signal for K and the data bus are electrically disconnected from the FIFO, and instead of the FIFO being controlled by the second CPU, a pseudo READ @ WRITE signal generated from the pseudo control signal generator of the first CPU is used. The FIFO can be controlled by the signal and the pseudo WRITE signal. Therefore, the second CPU is not operated at all and the FIF
It becomes possible to check the operation of O.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a FIFO self-diagnosis device that is an embodiment of the present invention. In FIG. 1, 1 and 2 each represent a CPU. 3.4 are FIFOs, and DBUS1, WR, R2, WR, and RL also have the same configuration as in FIG. 4. 6 is CPU 2,! :
11c exists between FIFO3 and FIFO4, and FIFO from CPU2
READ signal (R'2) for FO3,! :, FIF
WRITE signal (WR) to O4, CPU2 and F
This is a bus interface section for electrically disconnecting the data bus between the IFOs 3 and 4. 6 is from CPU1 to FI
READ signal (TR) for FOs and FIFO4
This is a pseudo control signal generator that generates a WRITE signal (TV) for the CPU.
This is for controlling PIFO instead of 2. 7
is the READ signal (
TR) and the READ signal (R1) from CPU2. Its output is sent to FIFO3 as RR.
connected to. 8 is the WRI T E signal (TW) from CPU 1 and W from CPU 2 to FIFO 4.
It is a gate that takes the logical sum of the RITE signal (Wl), and its output is connected to the FIFO 4 as WL. DBU
S3 is a data bus that connects the FIFo and the path interface section, and DBUS4 is a data bus that connects the bus interface section and the CPU 2. Also, the signal T is TR
This is a signal given from the CPU 1 to the pseudo signal generating section in order to create a TV. CLOCK is the CPU/CLOCK, and signal EN is the Gate signal of the bus interface section 6.

The operation of the FIFO self-diagnosis device configured as described above will be explained below with reference to FIGS. 1, 2, and 3.

First, when data is exchanged between CPU1 and CPU2 in normal operation, the bus interface section
The data bus and control signals are not separated from the FIFO, R1 and Wl are used for the control signals to the FIFO, and the same operation as in the conventional example is performed. C
Data exchange between the PU1 and the CPU2 can be performed in the same manner as in the conventional example.

Next, how can the above F I F be executed without the operation of CPU2?
We will explain how to check the operation of O.

First, the CPU 1 outputs the data to be transferred to the DBUS 1 and generates a WR multiplied signal for the PI FO 3.

As a result, the data on DBUS 1 is stored in FIFO3. Next, in order to take out this data from FIFO 3, conventionally the CPU 2 generates the R2 signal to FIFO 3, but in this embodiment, the data bus and control signals of CPU 2 are electrically disconnected from the FIFO and placed in a high impedance state. . Then, the pseudo control signal generating section of the CPU 1 generates a pseudo READ signal (TR) to the FIFO 3 and outputs the data stored in the FIFO 3 onto the DBUS 3. Next, while the data on DBUSa exists, a pseudo WRITE signal (TW) is generated from the pseudo control signal generator to FIFO4, and this
Data on Sa is stored in P I FO4.

Thanks to the above actions! It becomes possible to transfer the data stored in FIFO 3 to FIFO 4 without any operation of CPU 2. After that, RI for this FIFO4.

The FIFO operation check is completed by generating a signal K and comparing the data read by the CPU 1 with the data first output from the CPU 1 to the FIFO 3.

Here, using Fig. 2 and Fig. 3, from FIFO3 to FIFO
The specific timing of data transfer to O4 will be explained.

FIG. 2 shows a specific example of the pseudo control signal generator.

6-1.2 is a D-7 lip flop, T is a pseudo R
CLOCK is a control signal from CPU1 to generate the EAD signal (TR) and pseudo WRITE signal ('rw).
is CPU-CLOCK, and TR and TW are TR and TW (pseudo control signals) in FIG.

Figure 3 is a timing chart when data is transferred from FIFO3 to FIFO4, and Sl is the CPU/CLOCK
And S2 is the READ signal (RR) for FIFOsK.
Yes, S3 is data on DBUS S, S4 is FIF
6 with the WRITE signal (WL) to O4.

Below, to explain the timing of data transfer from FIFO3 to FIFO4, data in FIFO3 is transferred to DBUS.
When the control signal T is output from the CPU 1 in order to output S, the RR multiplied signal is generated in the FIFO 3 after the delay time of the OR gate 8 shown in Fig. 1, and the RR multiplied signal falls on the DBUS a as shown in Fig. 3. Determined data exists from start-up to start-up.

After the control signal T passes through the two 7-lip 70 tubes in FIG. 2, it is input to the FIFO 4 (C) as the signal (WL) at timing 84 in FIG. When the data on DBUSa is set up time,
The hold time is satisfied and the data is written to FIFO4.

Effects of the Invention As described above, the present invention provides a multi-C
In the PU system, by newly providing a bus interface section and a pseudo control signal generation section, the conventional FIF
The operation check of O used to be performed using two CPUs, but now it can be performed using only one CPU.
This greatly contributes to reducing software development and inspection man-hours when checking the operation of the FIFO, and the effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a FIFO self-diagnosis device according to an embodiment of the present invention, FIG. 2 is a logic diagram of a specific example of a pseudo control signal generating section, FIG. 3 is a timing diagram thereof, and FIG. 4 is a diagram of a conventional FIFO self-diagnosis device. 1 is a block diagram of a data exchange system between CPUs using FIFO. FIG. 1.2...CPU, 3.4...FIF
O16...Bus interface section, 6...
. . . Pseudo control signal generation section, 7, 8 . . . OR gate. Name of agent: Patent attorney Toshio Nakao and one other person
Figure 1 v142 Figure 31! I

Claims (1)

[Claims] A transmission/reception FIFO (Fast-i
n Fast-out Memory) and a control signal and data bus for the second central processing unit to perform read and write operations to the FIFO.
a bus interface unit for electrically disconnecting from the second central processing unit, and a pseudo control signal generation unit for generating from the first central processing unit a signal corresponding to the control signal generated from the second central processing unit. A FIFO self-diagnosis device characterized by comprising: