SU1059561A1 - Device for exchanging data - Google Patents

Abstract

1. DEVICE FOR INFORMATION EXCHANGE, containing microprogram memory block, RAM block, addressing block, RAM address register, multiplexer, data register, gateway block, register of instructions and priority block, The output of the addressing block is connected with the input of the programmable block of memory, the output of which is connected to the first inputs of the addressing block and the control inputs of the memory address register, the priority block P1 1, the multiplexer, the memory block, the register of instructions and the interface block and, the second input of the addressing unit is connected to the output of the priority block, the first group of inputs of which is connected to the input group of requests from device subscribers, the third input of the addressing unit is connected to the multiplexer output, the first information output of the interface unit is connected to the first input of the data register, the second input of which connected to the first information output — the RAM block, and the third input and the first output, respectively, with the input and output data; subscribers of the device, the second you; the data register course is connected to the first information inputs of the multiplexer and the RAM unit and the information input of the block, interface, the second information input of the multiplexer is connected to the first information output of the register of instructions, characterized in that, in order to expand the field of application of the device, the master machine control word register and the slave machine control word register group, the master machine control register information input connected to the second info the control unit of the interface block, the control input - with the control inputs of the control word registers of the slave MS-1 group and the output of the microprogram memory block, and the output with the first information input of the register of instructions, the information inputs (the register of the control word of the slave machine are connected with the information group of the outputs of the interface unit, and the outputs with the group of inputs of the data register, the group of outputs of the request of the interface unit is connected to the second group of inputs of the priority block, the second information output of the instructions tra connected to the address input interface unit, and; The Third Information Outlet - with the information input of the address register was co-operative; the first output of which is connected to the first address input of the RAM, O) the second output - to the third information input of the multiplexer and the second address input of the RAM, the third address the input of which is connected to the logical zero bus, the fourth address input to the first output of the memory address register, and the second information input and output to the fourth information input respectively and oromu data input of a register instruction, the group information and control inputs CIU are respectively

Description

data groups of control inputs of the device, the group of inputs of the mode of the interface block is a group of inputs of the mode of operation of the machines of the device,

2, The device according to claim 1, wherein the interface unit contains a switching node, a decoder, two groups of OR elements and a group of nodes of AND elements, the outputs of the OR elements of the first and second groups are connected respectively, with the first and second information outputs of the block, and a group of inputs, respectively, with the first outputs of the nodes of the elements of the group and the first group of outputs of the switching node, the second group of outputs of which is connected to the group of information outputs of the block and the group of inputs of the decoder, the group of outputs of which the group of outputs of the block request, and the input is connected to the second information output of the block, the group of address inputs of the communication node is connected to the group of inputs of the block mode, and the group of information inputs - with the second outputs of the node of elements AND of the group, the first, second and third inputs of which are connected respectively to the information, address and control inputs of the block, and the first and second inputs and outputs - respectively to the groups of information and control inputs and outputs of the block.

The invention relates to computing and can be used in multi-machine computing systems for the exchange between computers and subscribers. Communication devices for the computing system are known, comprising a synchronization unit, and in each channel receiving and transmitting registers, a comparison circuit, a pulse distributor, a control register, a node; synchronization, control node, address registers, status and three buffer registers, a group of OR elements and an output switch l. The disadvantage of these devices is large hardware costs. The closest to the proposed technical entity is an information exchange device containing an addressing unit, the input of which is connected to the output of a multiplex, whose inputs are connected to the data register, counter and instruction register moves, the main memory block and the main memory address register , priority block of connections with a group of device request inputs, a node of the conjugation, including a group of AND, OR, triggers and a read signal generation circuit, a microprogram memory block, whose outputs connected with the control inputs of the addressing unit, data register priority block PE1 istra instructions and interfacing node, a group of inputs-outputs of which are controlled gruppagli w boiling and information input-output device 2. The disadvantages of the known device are a large amount of equipment and limited functionality, which limits its scope. In particular, this device is designed for exchange with only two computers and is not able to provide exchange with external subscribers to the computer, for each computer in the device must be input and output registers and data counters. The purpose of the invention is to expand the field of application of the device by expanding its functionality and reducing hardware costs. The goal is achieved by the fact that a device containing a microprogram memory block, an RAM block, an allocation block, an RAM address register, a multiplexer, a data register, a gate block, an instruction register and a priority block, the output of the addressing block with the input of the firmware block, the output of which is connected to the first inputs of the addressing block and the control inputs of the address memory register register, priority block, niltiplexer, memory block, instruction register and block The second input of the addressing block is connected to the output of the priority block, the first group of inputs of which is connected to the input group of requests from device subscribers, the third input of the block (addressing is connected to the output of multiplexer1, the first information output of the interface block is connected to the first input of the data register, the second the input of which is connected to the first information output of the RAM unit, and the third input and the first output, respectively, with the input and output of the subscribers' data of the device, the second output of the data register of the connection The second information input of the multiplexer is connected to the first information output of the register of instructions, the control word register of the master machine and the group of the control word register of the slave main are entered, and the information input of the register the control word of the master lashina is connected to the second information output of the interface block, the control input is connected to the control inputs of the control word register ve Home Group machines and the output of the microprogram memory block, and the output with the first information input of the instruction register, the information inputs of the slave machine control word register 1 are connected to the information group of the output of the interface block, and the outputs with the input register group of data, the output group of the block request the interface is connected to the second group of inputs of the priority block, the second information output of the register of instructions is connected to the alias input of the interface block. and the third information output is with the information input of the RAM address register, the first output of which is connected to the first address input of the RAM block, the second output to the Third information input of the multiplexer and the second address input of the RAM memory, the third address input of which It is connected to the logical zero bus by the fourth address input - to the first OUTPUT of the register of the RAM address, and the second information input and output - respectively to the fourth information output and the second information The ion input of the register of instructions, the group of information and control inputs of the interface block are respectively the input-output-data groups and the group of control inputs-outputs of the device; the group-inputs of the mode of the interface block is a group of inputs the conjugation contains a knot, a decoder, two groups of the elements OR, and a group of nodes of the elements AND, and the outputs of the elements OR of the first and second groups are connected respectively with the first and second information outputs of the a, and groups of inputs, respectively, with the first outputs of nodes AND of the group and the first group of outputs of the switching node, the second group of outputs of which is connected to the group of information outputs of the block and the group of inputs of the decoder, the group of outputs of which is the group of outputs of the block request, and the input is connected to the second information output of the block, the group address-. A switching node is connected to a group of block mode inputs, and a group of information inputs are connected to the second outputs of node I group elements, the first, second, and third inputs of which are connected to the information, address, and control inputs of the block, respectively. the second inputs-outputs - respectively to the groups of information and control inputs-outputs of the block. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional scheme of the interface block; in fig. 3 - functional scheme of the multiplexer and addressing unit; in fig. 4 - enlarged algorithm of the device; in fig. 5 - exchange algorithm with the source subscriber; in fig. 6 - algorithm for issuing data to a computer. The device (Fig. 1) contains a conjugate block 1, a group of control word registers 2 of slave machines, a master machine control register 3, a data register 4, an instruction register 5, a priority block 6, a multiplexer 7, an operative block 8, a block 9 addressing unit, microprogram memory memory unit 10, register AND addresses of main memory, bus 12, device data input-output group, bus 13, device control input-output group, bus 14, device input group of device operation mode signs, bus 15; , bus 16 entrance data output of device subscribers, bus 17 of the group of requests for output of block 1, bus 18 of the group of information outputs of block 1, bus 19 of the first information output of block 1, bus 20 of the second information output of register 4, bus 21 of the address input and bus 22 of the second information block I, bus 23 of the first information output of the register 5, bus 24 of the output of the unit 10 and the line of control rooperations of the device. Interface unit 1 (Fig. 2) contains nodes of 25 elements AND groups, switching node 26, decoder 27, elements OR 28 and 29 of the first and second groups. Multiplexer 7 and microprogram addressing unit 9 (FIG. 3) contains modulo two convolution node 30, the first comparison circuit 31, the second

comparison circuit 32, third comparison circuit 33, element 34, register 35 modifying the address of a block of microprogram memory, node of elements AND 36, node of elements OR 37, register 38, the current address of a block of microprogram memory,

The device works as follows.

During the initial power-on, unit 10 closes all the registers and microcommands arriving on buses 24, continuously polls unit 6 before being detected. him for exchange invoice. The applications to block 6 are received from subscribers via bus 15 or from bus 17 from block 1. From the set of applications received at block 6 at various times, one is selected, the highest priority. According to the selected application from block 6, the OR of the 37 arrives K-times the starting address of the program of the 1st application service (exchange program) and is written to the register 38, From this moment begins and the execution of one of the many programs stored in block 10 The current addresses of the programs are received from block 10 via buses 24 through the elements OR 37 to register 38. Modifications of the current address are made by entering from block 10 through buses 24 to the register 35. Modification address and transferring this address through elements 36 and OR 37 to register 38 when the condition is met Mod generated by hardware 30 in ties les circuits 31-33 and Comparative through an OR gate 34.

Node 30 monitors the data words and, if the result of the convolution cannot be compared, it causes a conditional transition in the program.

The comparison circuit 31 compares the data word in register 4 with a constant, and the shi's input. We are 24 of block 10, and when comparing, it causes a conditional transition in nporpaiii. This is necessary to determine the end-of-text character of the data.

The comparison circuit 32 compares the address code of the last word of the subscriber data stored in register 5 and received on bus 23 with the current address code located in register 11. This is necessary to complete the exchange program if the data array is in the exchange program complete zone, and if the data array in the zone is shorter than the length of the entire zone when comparing codes, the comparison circuit 32 causes a conditional transition in the program at the time of the analysis micro-operations from block 10 via buses 24,

The Comparison circuit 33 compares the code of the current address located in register 11 with a constant received over the bus 24 of the highway from block 10 and indicating the code of the last address of the data zone. This is necessary for the protection of subscriber data zones in block 8 from overflows and bends. When comparing the codes, the comparison circuit 33 causes a conditional transition in the program,

The programs stored in block 10 provide the necessary time diagrams of the device operation in different exchange modes and trigger certain registers, keys and circuits by sending the necessary micro-operations pulses: Execution of the program allows you to receive a data array from any subscriber , inform the computer about which subscriber received the data and then issue it to any computer as instructed by the host computer; transfer the data array to the subscriber-consumer; receive data from the computer leading to the area of the memory cells, PE 1 belongs to the subscriber-consumer specified in the computer control word master, and then tell the computer that the subscriber is given; make an exchange with the slave computers on the instructions of the host computer, to which the control words received from the computer are previously sent. The latter type of exchange implies that all exchanges of the slave computers are conducted under the control of the host computer.

All types of the listed exchanges can be realized by selector or byte-multiplex modes, which is determined by the contents of control words received from the computer, by the programs stored in block 10, and by the contents of instruction cells stored in block 8,

The instruction cells are rigidly fixed in the first cells of block 8 for each subscriber and for each computer. In the instructions of the cells belonging to the subscribers, the service words that characterize the current exchange with each subscriber (the current byte number; a failure in the exchange, the total number of bytes in the array, a sign of failure, information in the zone, etc.,) are stored. computer instructions, cells of control words (CSS) coming from the respective computers, In this CSS, as well as for subscribers, there are various service signs that regulate the exchange program. The first action of each exchange nporpaMNDai is to read the corresponding instruction cell from block 8 and send its contents to the register 5 instructions. The contents of the instruction cell are stored in register 5 the entire execution time of the exchange program with this subscriber and is analyzed, modified or read by microoperations during the execution of the program . At the end of the current exchange program, the contents of register 5 are entered into the instruction cell of the corresponding subscriber in block 8.

In addition to the instruction cells in block 8, each subscriber is allocated a cell size of a certain size for cell exchange, with the base address of this zone most significant bits corresponding to the lower order bits of the address of the instruction cell belonging to the subscriber and the transition from the instruction cell to the base address of the subscriber data zone transferring the address code from the fourth to the first address input of block 8,

. Thus, at the beginning of each exchange program from block 10, buses 24 are registered in reg1; p 11 is entered into the address that is next to the quarter address of block 8 and together with the logical RN to the third address input of block 8, it reads the instruction cell. Then, after analyzing the contents of the instructions checks, which are in register 5, the program switches the address in register 11 to the first address input of block 8 and thereby ensures that the subscriber’s data zone is addressed. For example, to provide a device exchange with 63 subscribers and a computer, 6 bits are required for encoding in the lower bits of the addresses of the first 63 memory cells in which instructions will be stored. At the same time, in the higher bits of these addresses there will always be zeros. This implies that the first RAM area is allocated for service needs. The same 6 bits in the higher bits of the address with zeros in the lower bits determine the basic gap of cell zones for data exchange with subscribers and computers. With a memory capacity of 4096 cells and a 12-bit address, up to 64 bytes (or words) each will be exchanged with each of the 63 subscribers or computers. With an increase in the number of subscribers and computers, an increase in the number of address bits is required to indicate instruction cells. To increase the data arrays of Tpie, an increase in the capacity of the RAM is required. .

The procedures described above are depicted in FIG. 4 in the form of an integrated algorithm.

The device allows to realize various types of exchange between subscribers and a computer, for example, an exchange with a source subscriber operating in multiplex mode, the algorithm of which is shown in FIG. 5. Each element of the algorithm (conditional or unconditional action) is a microt command or a group of micro-instructions consisting of micro-operations. The device at each moment of time realizes the exchange with one of the subscribers or with one of the computers. At the same time, in the operative memory of the device, there may be complete or incomplete arrays of information of other subscribers waiting for their exchange queue. Simultaneously, in block 6, exchange requests received from other subscribers and computers are received. Selective application for the implementation of the exchange is made only after the completion of the order exchange. In this way, various conflict situations are eliminated. Interruption of exchange in the device is not provided.

0

Each computer is exchanged via block 1. The initiative is exchanged by each computer, asynchronously with respect to the operation of the device, sending a control word on its bus 12 accompanied by a control signal on bus 13. Pass through the elements AND the corresponding node 25, the control word is transferred via switch node 26 to

0 corresponding register 2 or through the elements OR 29 to the register 3. Registers 2 from 4 times the MS from all the slave computers, and to register 3 from the registers from the host computer. Since the leading computer

5 there can be only one, and any computer, then the indication which computer is leading from outside is produced by positional signs on tires 14, one of which is always different from the others. Signs for tires 14

0 arrive at the switching node 26 and indicate to the US what computer to send to the register J. Each control word passes through the decoder 27 and turns into a jam, which

5, bus 17 enters block 6, where it waits for service.

When executing computer exchange programs, the data received from the computer and sent to the computer via tires 12 passes through nodes 25. The output to the computer of data words is preceded by sending a control signal to tires 13 (input requirement in Fig. 6), then from the computer on tires 13 arrives

5 response control signal, valveing the corresponding element And node 25 and allowing the passage of data from register 4 through bus 20 through bus 12 data of the corresponding computer.

0 When receiving data in the same way, a signal is sent to the computer via bus 13 (output requirement), in response to which from the computer via bus 12, node 25, valveing the control signal accompanying data via bus 13, and through

five

element OR 28 in the bus 19 enters the word data. The algorithm for issuing data words to a computer is shown in FIG. 6

The exchange with the subscribers, the input and the reception of the data word are made via the data buses 16 and the register 4 with a hard time synchronization, for example -lak, as a similar mode is realized when using a mono channel in local data exchange systems. On fil. 5 shows the exchange algorithm with the source subscriber; the algorithm elements that ensure the interaction of the exchange device with the subscriber are highlighted with a double line. There are other ways to synchronize the exchange with subscribers.

Thus, the proposed device for the exchange of information between the computer complex, state 2

j

sh

and.

one

Ll

(Ji 1

and with F

/ h i

Jj

f6 ±

 G4-L

9 / D ... T / aX /

17

G ... g

 i

Ш4 / г /

It is possible to expand the functional capabilities and, consequently, the field of its use with lower hardware costs as compared with the prototype type. The introduction of control word registers for computer computers allows all computers to asynchronously send control words from which exchange applications are formed, waiting for the exchange to start. The exchange with the computer is carried out taking into account the contents of the controllers, words, and equipment such as a data register is used universally for all exchanges. The content of the control word 5 can indicate the type of exchange and the subscriber or computer with which exchange is desired, which allows to expand the possibilities of organizing various exchange Q transmissions of information.

H

6

i.l

//

23

3 k

f

P

T

"L

Sj

"Si

-

"S

sr

R

K &

g f v

t

31

. thirty

Tz

25

Block 0

24

I

yj}

32

33

I

/

OmPrff

Start the inclusion and (setting o, o all register device

Exchange program availability

fefiniiteteiiiH tft II "phga ynet tsytsib

Scriptures on the sidelines m lcmpyk tti

vfatiHif SftHeafeceofii - daitmat agM ll

 VMrffyKf tMtftepeiatinfaj PtS

It grew from evento vierednaev beyt YRrg11

 UHipofHauuu from subscriber S Rg

esumnak eshts

VMMfv iMemfjffiiM I

iffiHJA

you 3 prvgranmy

fopHupoeaMf head address in the aeroramma

Formating of Prog Nadresy imgtruhtsii cells

Readings uyhih instructions on Pr5

Sttybamie infdrnatsaa

y.0f9f / from ilok 81 register,

Bxo9 program

census of oOftiStPeS

U, d ReZ; 9stRgU census feature

ace

J

I

WfM.M, 9tn

Thr

macaw

BuxaS of arvgrvty

I ULRGZ

Farmirvyamy dlv38 (Bosh. With chzhevny cmia ltd.

La

vyvvchavZVN service

Figb

Claims (2)

1. DEVICE FOR INFORMATION EXCHANGE, comprising a microprogram memory block, a RAM block, an address block, a memory address register, a multiplexer, a data register, a pairing block, an instruction register and a priority block, the output of the address block being connected to the input of the microprogram memory, output which is connected to the first inputs of the addressing unit and the control inputs of the RAM address register, priority block, multiplexer, random access memory block, instruction register and interface block, second the first input of the addressing unit is connected to the output of the priority unit, the first group of inputs of which is connected to the group of input requests from the device's subscribers, the third input of the addressing unit is connected to the output of the multiplexer, the first information output of the interface unit is connected to the first input of the data register, the second input of which is connected to the first information output · RAM block, and the third input and the first output, respectively, with the input and output of the data of the subscribers of the device, the second output, the output of the data register is connected to the first by the input inputs of the multiplexer and the RAM unit and the information input of the unit, the interface, the second information input of the multiplexer is connected to the first information output of the instruction register, characterized in that, in order to expand the scope of the device, the control word register of the host machine and the group of control registers are introduced into it words of the driven machine, the information input of the control word register of the master being connected to the second information output of the interface unit, controlling one - with the control inputs of the control word registers of the slave machine of the group and the output of the firmware block, and the output with the first information input of the instruction register, the information inputs of the control word register of the slave machine are connected to the information group of the outputs of the interface unit, and the outputs - with the group of inputs of the data register, the group of request outputs of the interface unit is connected to the second group of inputs of the priority unit, the second information output of the instruction register is connected to the address input of the interface unit, and. the third information output - with the information input of the RAM address register, the first output of which is connected to the first address input of the RAM block, the second output - with the third information input of the multiplexer and the second address input of the RAM block, the third address input of which is connected to the logical zero bus, the fourth address input to the first output of the RAM address register, and the second information input and output, respectively, to the fourth information output and the second information ion entry register 'instructions, the group information and control interface block inputs are respectively> As a result of the groups of data input-output and the group of control inputs of the outputs of the device, the group of inputs of the mode of the interface unit is the group of inputs of the signs of the operating mode of the machines of the device. 2. The device according to claim 1, the fact that the interface unit contains a switching node, a decoder, two groups of OR elements and a group of nodes of AND elements, and the outputs of the OR elements of the first and second groups connected to the first and second information outputs of the block, respectively, and the input groups, respectively, to the first outputs of the nodes of the AND elements of the group and the first group of outputs of the switching node, the second group of outputs of which is connected to the group of information outputs of the block and the input group of the decoder, the output group of which is the output request group of the block, and the input is connected to the second information output of the block, the group of address inputs of the switching unit is connected to the group of inputs of the mode of the block, and the group of information inputs is connected to the second outputs of the node of elements AND groups, the first, second and third inputs which are connected respectively to the information, address and control inputs of the block, and the first and second inputs of the output, respectively, to the groups of information and control inputs of the outputs of the block.