SU1355977A2 - Memory addressing device - Google Patents

Abstract

The invention relates to the field of computing and can be used to address memory blocks in a digital computer. The aim of the invention is to expand the scope by managing the organization of the memory. The device contains a group of 1 switches, a group of 2 adders, a group of 3 comparison elements, a group of 4 memory blocks, a group of 5 decoders, a group of 6 switches. The device has the ability to organize a variable memory size with a corresponding change in its capacity. 1 il. with V Coe / vcr / r e / r / ffrrt / p TrfrjfuftMt aafyec yCfn / fff Jf fo (с s: co wore SL CO VI VI Xvfu / ae atffmfMdif ffOUO / N)

Description

The invention relates to computing technology, can be applied for the addressing of memory blocks in a digital computer, and is an improvement of the device according to the author. No. 1298755.

The aim of the invention is to expand the scope by managing the organization of the memory.

The drawing shows a block diagram of the device.

The device contains a group of 1 switches, a group of 2 adders, a group of 3 comparison elements, a group of 4 memory blocks, a group of 5 decoders, a group of switches 6.

The device works as follows.

After a continuous address field of the memory system is set at the outputs of all of the accumulators 2 corresponding to the disconnected memory blocks 4, the device starts operating in the main sampling mode of the memory block 4.

If the change signal of the organization (structure) of the memory of the system is absent, the device works without changes, i.e. When accessing the memory, the comparison elements 3 compare the addresses from the outputs of the adders 2 and the address buses. If the address at the second output of the i-ro of the adder 2 matches the address from the input of the current address of the memory system on the i-M comparison element 3, a signal appears when it arrives at the control input of the t-ro storage unit, i.e. the access occurs to the i-th block 4 of the memory. The input and output information from the output of the i-ro of memory block 4 passes through a single information channel of the memory system.

After the arrival of the signal of change in the organization (structure) of the memory, it is fed to the control inputs of the decoder 5 and to the second control inputs of the comparison elements of group 3, preparing the decoders for operation and disconnecting the three lower-order bits of the comparison elements of group 3 with the outputs of the corresponding adders 2, Then in the sampling mode of the memory block 4, the comparison of the addresses coming from the outputs of the corresponding adders 2 and the address buses is done without the least significant bits, i.e. Only for disconnected senior developers. In the

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In addition to the coincidence at the outputs of the 1st, (i + 1) -ro ... (1 + 7) -th elements of the 3rd comparison group, signals appear that go to the control inputs of the corresponding memory blocks 4.

Thus, the access occurs simultaneously to eight blocks of 4 memories. In addition, signals from the outputs of the selected comparison group elements 3 appear at the second control inputs of the respective decoders and are allowed to decrypt the incomplete junior address arriving at the information inputs of the decoders 5 of the group from the three lower-order outputs of the corresponding adders 2.

On one of eight decoders of the 5th group, signals appear that arrive at the switching elements corresponding to these decoders and open them, closing the outputs of eight selected memory blocks with one of the five eight information channels, the output of the i-ro memory block 4, having i-ro adder 2 on three least significant bits of i-ro is connected to the first information channel, the output (i + 1) -ro of memory block 4, having the address of the three least significant bits (i + 1) -ro of adder 001 is connected to the second information channel, etc. The output of the eighth selected memory block 4 having the address of the three small output bits of the corresponding adder 2 111 is connected to the eighth information channel of the external computing system.

Thus, at the moment of sampling of memory blocks 4, access does not occur to one i-th memory block 4, but to eight memory blocks at once, the outputs of which are connected not to one, but to eight information channels of you

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 numeral system.

Claims (1)

Formula from a shadow of a shadow. Device for memory addressing according to auth.St. No. 1298755, characterized in that, in order to expand the field of application of the device due to the possibility of memory reconfiguration, a group of decoders and a group of switch blocks are introduced in it, the first inputs of the group decoders are connected to the lower block inputs of the corresponding elements of the group and with signal input  1355977 reconfiguration of the device memory, blocks of switches of the group, the second the second, third entrances of the decoders, the inputs and outputs of which are connected are the groups connected respectively to the input of the device for By comparing the elements of the group and connecting the output of the data to the memory block with the outputs of the three lower-order bits of the sum and the output of the device for submators of the group, the outputs of the decoder include external information groups that are connected to the first inputs and channels.