SU1376224A2 - Two-phase shaper of harmonic signals - Google Patents

Abstract

Invention m. Used in tests of systems with quadrature signal processing. The scope of the invention is the expansion of the frequency range of the output harmonics, signals. Gd contains multivibrator 1, distributor 2 pulses, blocks 3 and 4 keys, low-pass filters 5 and 6, a multilevel source of 7 constant voltages. Introduced El-8, the shaper code (FC) 9, Mr. JO of single pulses. FC 9 contains a reversible counter, EL OR, two decoders, a cumulative register, a block of elements I. Smoothing of step-varying quadrature signals from the NAL outputs, which contain blocks 3 and 4 and source 7, is produced by filters 5 and 6, Expansion of the frequency range of the output harmonic. signal fishing is done by diminishing. staging level discrete signals. 1 hp f-ly, 2 ill. i (L

Description

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The invention relates to radio engineering and communication, measurement technology, can be used for testing systems with quadrature signal processing and is an improvement of the invention according to the author. St. No. 1084941.

The purpose of the invention is to expand the frequency range of the output harmonic signals.

Figure 1 shows the structural electrical circuit of a two-phase harmonic generator; Figure 2 is a structural electrical driver circuit diagram.

A two-phase harmonic generator contains (Fig. 1) multivibrator 1, a distributor of 2 pulses, a block of 3 keys, an additional block of 4 keys, a low-pass filter 5 (LPF), an additional LPF 6, a multilevel constant voltage source 7, element 8, shaper 9 code and generator 10 single pulses.

The shaper 9 code contains (figure 2) reversible counter 11, the element OR 12, the first 13 and the second 14 de vfritory, cumulative register 15 and a block of 16 elements AND,

Two-phase harmonic generator works as follows.

For tuning the frequency of the output harmonic signals, the multivibrator 1 is adjustable in a wide frequency range, and starting from a certain subrange, single pulses are applied to the summing and subtracting 1 inputs of the reversing counter 11 from the generator output 10 of single pulses, changing the tuning frequency code. If the multivibrator switch 1 moves in the direction of increasing frequency, the pulses are fed to the summing input of the reversible counter 11, and vice versa, if the switch of the subbands moves in the direction of decreasing frequency, the number of pulses is proportional to the number of switches of the subband switch. At the same time, through the element OR 12, single pulses arrive at the input of the installation of the cumulative register 15 to the initial state. The codes from the output of the reversing counter 11 are decrypted by the first entree 13, entered into the cumulative register 15, simultaneously decrypted by the second decoder 14, and fed to the input of the 16-unit I. As the clock pulses from the output of the multivibrator 1 arrive recorded from the output of the first decoder 13. As soon as the highest bit of the output of accumulative register 15 turns on logical 1, a logical O is output at the overflow output, as a result With this, the arrival of clock pulses through the AND element 8 is terminated. The storage register code 15 is fed to the inputs of the pulse distributor 2, which serves as an element of the buffer memory for digital-to-threshold converters, which contain block 3, additional block 4 and a multi-level source 7 of constant voltage. Smoothing of step-varying quadrature signals from the outputs of digital-to-analog converters is performed by the low-pass filter 5 and an additional low-pass filter 6, and the frequency range of the output harmonic signals is expanded by decreasing the sampling levels of the step-changeable signals.

Claims (2)

1. Two-phase harmonic signal generator according to ed. St. No. 1084941 characterized in that, in order to expand the frequency range of the output harmonic signals, a single pulse generator, a serially connected code generator and an AND element are introduced, with the first and second outputs of the single pulse generator connected to the summing and subtracting inputs / code generator, each of the bit outputs of which are connected to the corresponding additional bit input of the pulse distributor, the synchronizing input of the code generator is connected to the output element The input is And, the second input of which is connected to the output of the multivibrator, and the input of the single pulse generator is connected to an additional multivibrator. 2. The generator according to claim 1, about tl and - due to the fact that the code driver contains a sequentially connected reversible counter, a first decoder and a cumulative register, the second decoder and the block of elements AND in series and the OR element whose output is connected to the installation input cumulative register, the information input of which is connected to the output of the block of elements AND, the first and second inputs of the element OR are connected respectively to the summing and subtracting inputs of the reversible counter, each of the bit outputs which soedi- nen to a corresponding input of the second decoder, each of the inputs of the second the group of inputs of the block of elements I is connected to the corresponding bit output of the cumulative register, the summing and subtracting inputs of the reversible counter being respectively the cmming and subtracting inputs of the code generator, the synchronizing input of the cumulative register being the synchronizing input of the code generator, The output of the code generator, the bit outputs of the cumulative register in the output of the code generator generator. § With vymda §lock S 2Fig.2