SU703920A1 - Device for receiving address call - Google Patents

Description

I

The invention relates to radio engineering and can be used in devices for making and receiving a selective call.

A device for receiving an address call, containing a switch, a signal converter, a clock generator and a decoder, the output of which is connected to another output of the signal converter, the output of the comparator through an integrator connected to the input of the display unit and the second output of the clock generator through serially connected, is known. the frequency divider and the OR element is connected to the input of the control register, the output of which is connected to the input of the switch and to another input of the ifratora 1.

However, the known device has a rather high probability of false positives, which reduces the reliability of its operation.

The purpose of the invention is to reduce false positives.

For this purpose, the device for receiving an address call, containing a series-connected switch, a signal converter, a clock generator and a decoder, the output of which is connected to another output of the signal converter, the output of the comparator through the integrator is connected to the input of the display unit, and the second output of the rejiepaTopa clock pulses serially connected frequency divider and the OR element is connected to the input of the control register, the output of which is connected to the input of the switch and to another input of the desh Rathore, introduced

bistable element, the element And the element of the reset, while the other output of the integrator through a bistable element is connected to the first input of the element And, the second input of which is connected to another output

the divider of the device, the output of the AND element is connected to another input of the OR element, the output of which through the reset element is connected to other inputs of the integrator and the frequency divider, and the output of the integrator is connected to the auxiliary input of the OR element.

Claims (2)

The drawing shows a structural electrical circuit of the proposed device. The device for receiving an address call contains a switch 1, a control register 2, a signal converter 3, a clock generator 4, a decoder 5, a comparison unit 6, an integrator 7, a bistable element 8, a display unit 9, a frequency divider 10, an AND 11 element, an OR element 12 and the reset element 13. The device operates as follows. The outputs of the analyzed channels of a multi-channel communication system, the signals of which are represented as a code sequence of two tonal frequencies, are alternately connected to the input of the converter 3, which forms - according to the incoming information, certain pulse sequences that arrive at one of the two inputs of block B is also used to synchronize the phase of the generator 4, which is also a clock generator for the decoder 5 connected to the second input of the block 6. Operation and operation switch 1 and the change code sequences arriving from the output of the decoder 5, is provided by the control register 2. Clock pulses for control register 2 are formed by frequency divider 10, the first output of which is connected to the input of the OR element 12, and the second output is connected to the input of element 11 of the second input of which is connected to the bistable element 8. Frequencies The clock pulses from the first and second outputs of frequency divider 10 are significantly different, i.e., the first output of frequency divider 10 is intermediate with respect to the second, therefore two sequences of clock pulses can be sent to control register 2: per WA with frequency f and second with frequency Nf. Block 6 compares the received code sequence with the code sequence coming from the output of the decrypter of Rotor 5. The comparison of the code sequences is performed impulsively. The coincidence of each pair of pulses is fixed in the integrator 7. The results of the integration are fed to the input of the bistable element 8. If the integration of the address characteristic inherent in this channel does not detect the incoming signals (i.e. are received), then from the second integrator 7 to the bistable element 8 a control voltage is applied: the transferring bistable element 8 to the bank of steady states, characterized by issuing the inhibiting signal to the first input of the element 11, on the second input of which at this time receives pulses from the second output of frequency divider 10. As a result, the signals on both inputs of the AND 1 1 element act and it triggers through the OR 12 element to control register 2 a signal that means the analysis of the channel is stopped and the analysis next one. ....: ..V In addition, the signal from the output of the element OR 12 is supplied to the reset element 13, which generates a reset pulse, which ensures that the integrator 7 and frequency divider 10 are transferred to the zero (initial) state, which prevents false operation of the device when analyzing the next channel due to the presence in the integrator 7 of residual information about the results of the analysis of the previous channel and ensures reliable operation of the device. If the pre-integration results are positive, i.e., the address written in the decoder begins to coincide with the incoming code sequence, then from the second output of the integrator 7 to the bistable element 8 the control voltage is not applied and it remains there. the steady state, which is characterized by the prohibition signal being sent to the first input of the element 11. As a result, the element II does not work, the signal to the control register 2 is not received from its output and the analysis of this channel continues. After the interval of time required for full integration, the signal from the first output of the integrator 7 is fed to block 9 and through the OR element 12 to the control register 2, which ensures the device goes to the next channel analysis. The functions of the reset element 13 in this case are similar to those considered above. If the results of the pre-integration are positive, and full integration due to any reasons does not occur, then the device is switched to the analysis of the next channel forcibly. . The invention The device for receiving an address call, containing in series a switch, a signal converter, a clock generator and a decoder, the output of which is connected to another output of the signal converter, the output of the comparator unit through the integrator is connected to the input of the display unit, and the second output of the generator of clock pulses through the serially connected frequency divider and the OR element is connected to the input of the control register, the output of which is connected to the input of the switch and to others The opposite input of the decoder is characterized in that, in order to reduce false positives, a bistable element, an element AND and a reset element are introduced, while another integrator output is connected to the first input of the element I through the bistable element, the second input of which is connected to another output of the frequency divider, output element And connected to another input of the OR element, whose output through the reset element is connected to other integrator inputs and a frequency divider, and the integrator output is connected to the auxiliary input of the OR element. Sources of information taken into account in the examination 1. Copyright certificate for application No. 2409146, cl. H 04 Q 5/00, 1976 (prototype).