SU1132365A1 - Device for executing "logical equivalence" operation based on ferrite-ferrite ternary elements - Google Patents

Abstract

DEVICE FOR PERFORMING THE OPERATION OF THE LOGICAL FLEXIBILITY ON FERRITE-FERRITE TRILIOUS ELEMENTS, containing the first ternary element and the second ternary element having the first second, third and fourth inputs, two information and clock buses, the first and second inputs of the first ternary element are connected respectively to the first and second information tires, characterized in that, in order to increase reliability, the first ternary element is made two-input, the clock bus is connected to the first input of the second ternary element the third and fourth inputs of which are connected to the output of the first ternary element. E ND E z: U1 fui.l

Description

The invention relates to computing and can be used in the design of highly reliable logical nodes of information systems on logic elements with pulse inputs and outputs that are resistant to the effects of pulsed magnetic and electrical noise.

A device for performing a logical inequality is known, which contains two ferrite transistors.

A disadvantage of the known device is its relatively low reliability, since each element contains a transistor and a ferrite core.

A device for performing a logical equivalence operation on ferrite-ferrite ternary elements is known, comprising two ternary elements having first, second third and fourth inputs, two data and clock buses, first, second and fourth inputs of the first ternary element connected respectively to the first, second information and clock tires, the first, second inputs of the second ternary element connected to the output of the first input ternary element t2.

Each of the elements performs the operations listed in Table 1. Elements form a functionally complete system of logical functions.

Table 1

A disadvantage of the known device is that it has LOW reliability19, since it is made on twelve ferrite cores, since each of the two four-input ferrite-ferrite ternary elements contains six ferrite cores.

The purpose of the invention is to increase the reliability of the device.

60 To achieve this goal, the device for performing the operation is logical equivalence on ferrite-ferrite ternary elements containing the first ternary 65 element and the second ternary element.

having the first, second, third and fourth inputs, two information and clock buses, the first and second inputs of the first ternary element are connected respectively to the first and second information buses, the first ternary element is made two-input, the clock bus is connected to the first input of the second ternary element, the third and the fourth inputs of which are connected to the output of the first ternary element.

In the first ternary element, as compared with the second ternary element, there are no two entrances (second and third) and therefore only the first, second, ninth and tenth paragraphs of Table 1 are valid for the first ternary element. The first ternary element can be built on four ferrite cores.

Figure 1 is a diagram of a device for performing a logical equivalence operation on ferrite-ferrit ternary elements; Fig. 2 is a timing diagram of its operation with the conventions for the examples presented in Table 2.

In FIG. The device for performing the logical equivalence operation on ferrite-ferrite ternary elements comprises first and second ternary elements 1 and 2, respectively, first and second information buses 3 and 4, respectively, clock bus 5, output bus 6.

Tires 3-6 are connected respectively to the first input of element 1, the second input of element 1, the first input of element 2 and the output of element 2, and the output of element 1 is connected to the second and fourth inputs of element 2.

FIG. 2 denotes: timing diagrams of 7, 8, and 9 clock pulses, respectively, on tires of the first, second, and third phases of the clock supply of the device; timing charts of 10 and 11 signals, respectively, n tires 3 and 4; timing diagrams of 12 and 13 signals, respectively, at the outputs of elements D and 2.

The clock supply system of the device is three phase; signals (positive or negative) on buses 3-5 are received during the clock pulse of the first phase, the clock pulse of the second and third phases reads the information from elements 1 and 2, respectively. Bus 5 always receives signals with a frequency of the clock power of the device from ferrite-ferrite tro elemental ban or from the bus of the first phase of the clock litany of the device.

The operation of the device is described in the examples presented in Table 2.

5 In example 1, a clock signal of the first phase of the first clock cycle receives a positive signal on bus 5, which is transmitted to the first input of element 2 and is written to the black (see tab.1), the clock pulps of the second and third phases are read from elements 1 and 2, respectively. Zero and positive signals (a positive signal is fed to bus 6). Similarly / according to the scheme (figure 1) and the time diagram (figure 2), the following examples shown in table 2 are executed.

Table 2.

0

35

40

Thus, the use of a double-ended ternary element in the proposed device with a corresponding change in the design features made it possible to reduce the total number of ferrite cores, which increases reliability compared to the device-prototype.

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Claims (1)

DEVICE FOR PERFORMING THE OPERATION `` LOGIC IDENTITY '' ON FERRITE-FERRITE TRINITY ELEMENTS, containing the first ternary element and the second ternary element having the first "second, third and fourth inputs, two information and clock buses, the first and second inputs of the first ternary element respectively, with the first and second information buses, characterized in that, in order to increase reliability, the first ternary element is made two-input, the clock bus is connected to the first input of the second ternary element, rety and fourth inputs of which are connected to the output of the first ternary element.