SU1350843A1 - Device for regenerating digital signals - Google Patents

Abstract

The invention relates to radio engineering and increases the noise immunity from intersymbol interference, the device contains an input amplifier 1, a corrector 2, an adjustable artificial line 3, an amplifier 4, a decisive block 5, a filter-selector filter 6 clock frequency, a phase shifter 7, an output block 11. Reintroduced control unit 8, block 9 counters, output code generator 10. 6 Il. f2f-4 (L 00 ate about 00 4 00 (pi / .f

Description

The invention relates to electrical engineering and can be used to regenerate a digital signal.

The purpose of the invention is to improve the noise immunity from intersymbol interference.

Fig. 1 shows a structural electrical circuit of the device proposed; figure 2 - block diagram of the decision block; FIG. 3 is a block diagram of the control unit; in fig. 4 - block diagram of the meter block; FIG. 3 is a block diagram of an output code driver; 6 shows timing diagrams for the operation of the device.

The digital signal regeneration device contains an input amplifier 1, an equalizer 2 regulating the artificial line 3, an amplifier 4, a decisive block 5, a filter frequency selector 6, a phase shifter 7, a control block 8, a counter block 9, an output code driver 10 , output unit 11. In this case, the decision block 5 consists of comparators 12 and 13, the element OR 14 and trigger 15, the control block 8 consists of shapers 16 and 17 short pulses, the element EXCLUSIVE OR 18, triggers 19 and 20, elements AND 21-26, element OR 27, block 9 counters consists of Meters withstand 28 and 29, the output code generator 10 is composed of flip-flops 30-32, OR gate 33, NOT elements 34, AND gates 35 and 36, the AND-OR-NO element 37 and 38.

The device works as follows

The digital two-level signal (Fig. 2b) is fed into a narrow-band linear path with a bandwidth of approximately 0.25. From the path output, the distorted signal enters the analog part of the regenerator (input amplifier 1, equalizer 2, adjustable artificial line 3, amplifier 4) where the corrected and amplified signal is amplified and corrected (fig. 6b) to the input of decision block 5, where it is converted into logic levels (fig. 6c).

Voltages ± U are selected in such a way that they allow one to get rid of low-power high-frequency interference and a constant component caused by zero-level oscillations (Fig. 6b: Signals from the second output of a comparator).

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Ditch 12 and 13 are combined using the OR 14 element and enter the short pulse generator 16 of the control unit 8, where short pulses are generated on the falling edges of the signals received from the comparators (Fig. 6e).

The filter-selector 6 clock frequency restores the clock frequency of the original signal (Fig, BE), and the phase shifter 7 sets the phase clock. pulses relative to the output signal of the main amplifier in such a way that they fall into the middle of the signal interval generated by the comparator unit in a group of three categories of the following symbols of the same name and shifted by I80 relative to the center of a group of two blocks of the next symbols of the same name (Fig. 6g). Moreover, this ratio remains constant regardless of the structure of the code combination.

The pulses generated by the short pulse generator 16 of the control unit 8 are supplied to a distribution circuit consisting of AND 21 and 22 elements, trigger 20, EXCLUSIVE OR 18 element, short pulse generator 17, and OR element 27, B depending on trigger state 20 pulses either the fifth or the first and sixth outputs of the control unit 8 are received. After the distribution scheme, the pulses arrive at the write inputs of counters 28 and 29 (fig. 6h, and) of the counter block 9 and the synchronous inputs of the trigger codes 30 and 31 of the output code generator 10, who serve d storing sign generated trigger 15 deciding unit 5 (FIG. 6d). Thus, the sign of the input information sequence (1 + O -) is recorded in the memorization triggers of the sign, and the code of the number 2 in the counter 28 or 29 of the counter block 9.

As only the code of the two is written into one of the counters, at its transfer output there appears a unit that enters the output code generator 10 on the I 35 and ZGz elements and permits the passage of the mark on the I-IL11-HO 37 element. the signal from the output of the counters is fed to the inputs of the trigger 19, the EXCLUSIVE OR 18 element, the AND elements 25 and 26 of the control unit 8. Using these elements, the clock signal is alternately connected to the subtractive inputs of counters 28 and 29 of the counter block (fig. 6k, l). After the passage of the second clock pulse, the counter 28 is set to O (FIG. 6m) and this signal prohibits the passage of clock pulses to its input. In addition, with the same signal, trigger 20 of control block 8 is transferred to a new state, which makes it possible to pass a pulse generated by shaper 16 short pulses to the input of the counter 28 of block 9 counters, and the clock pulses into IT time at the counter 29 (Fig. 6 l). In this way, the counters work alternately, and the inputs of the AND-OR-HE element 37 of the output code generator 10 of the output code are fed either O or 1 for two cycles depending on the sign of the input information sequence.

The output of this block of information passes through the control signals from the output of the trigger 20 of the control block 8, which is switched by the control signals from the transfer outputs of the counters 28 and 29 of the block 9 of the counters. From the output of the I-11PI-37 element of the output code conditioner the input element is AND-OR-NOT 37 and passes to the output only when the input information sequence contains two or three lines of the same information characters. If there are no such combinations, which corresponds to the signal 101010 in the information sequence on the transmitting side, then the AND-OR-HE element 38 passes to its output the signal from the trigger 30, which ensures the formation of the meander in the output sequence. The AND-OR-38 element is switched using the OR-33 element and the HE-34 element, and the control signals are signals from the transfer outputs of counters 28 and 29 of the counter block 9. The trigger 30 generates an output information signal with a duty cycle of 1. Moreover, the trigger operation is organized in such a way that when a signal arrives there are no two or three sets of information symbols, the state opposite to the previous one is formed at its output. This ensures the joining of two or three additional characters (a write pulse to the counter (FIG. 6c-o), corresponding to three further characters, arrives when the second counter is already zeroed, t, e, there is no signal

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and the track that translates trigger 5

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the ger into the state opposite to the previous one, i.e. the first symbol of the three and the meander formation are formed.

Claims (1)

Invention Formula A digital signal regeneration device containing a serially connected input amplifier, an equalizer, an adjustable artificial line, an amplifier and a deciding unit, as well as an output unit, a clock filter filter, the output of which is connected to the input of the phase shifter, and the first output of the amplifier is connected to the filter input - clock frequency selector and the second output of the amplifier is connected to the second input of an adjustable artificial line, characterized in that, in order to improve noise immunity from intersymbol interference introduced control block, counter block and output code driver, with the first output of the decision block connected to the first input of the control block, the first, second, third, fourth and fifth outputs of which are connected to the first, second, third, fourth and fifth the inputs of the meter block, the sixth, seventh, eighth and ninth outputs of the control unit are connected respectively to the first, second, third and fourth inputs of the output code generator, the fifth, sixth, seventh, eighth and ninth inputs of which are connected respectively etstven-; but with the fifth output of the control unit, the first, second outputs of the counter block, the output of the phase shifter and the second output of the decision block, the output of the phase shifter is connected to the second input of the control unit, the third, fourth and fifth inputs of which are connected i respectively to the first output of the output code generator, the first, second outputs of the meter block, the second output of the output code generator is connected to the input of the output block. about 15 T ig.2 g: G6 I 21 2Z "at L. eight 23 25 2U guv J WITH Co - / 29 (Fig.  g I. 5 9 aa a 6 g § BF 3 and to l m n o P П П П П П ni П П П П П П П П, П ri p p p p p p p rii p p p p ggi-p p p l ... jl l ..... pn . „Lzl. P (7 one ... x l pn P (7 F1 / g: