SU1356240A2 - Device for checking authenticity of information transmission by quasiternary code - Google Patents

Abstract

The invention relates to telecommunications and improves the accuracy of control in communication channels with error batching. The device contains expr 1, elec-RSh 2, 12, 17, 3 clock frequency selector, electr-4 and 13, triggers 5 and 14, shift registers 6 and 7, electr And 8, 9, 19, 20, shaper 10 clocks, counter 11. Al-16 or 16 again entered. E-mails And 21 and 22. The allocator 3 is implemented as a generator with phase locked loop. 1 hp f-ly. 2 Il. (L: SP and K 4)

Description

The invention relates to telecommunications and can be used in the construction of devices for controlling the reliability of information transmission by a quasi-terrestrial code in digital communication channels and is an improvement of the invention according to the author. St. № 1177921 ..

The purpose of the invention is to increase the control accuracy in communication channels with error batching.

The drawing shows the structural electrical circuit of the device for controlling the reliability of transmission

information with quasi-coded code. I

The device for controlling the reliability of information transmission quasitroich Hb iM code contains rectifier 1, the first element OR 2, the clock 3 frequency selector, made in the form of a generator with phase auto-tuning frequency, the first element is NOT A,: First trigger 5, first and second registers 6 and 7 shift, the first and second elements And 8, 9, shaper 10 clock pulses, counter 11, the second element OR 12, the second element NOT 13, the second trigger 14, the third and fourth elements And 15, 16, the third and fourth elements OR 17, 18, fifth, sixth, seventh and eighth element s 19, 20, 21 and 22.

The device works the following way.

The quasi-Troichan signal input to the device is divided by rectifier 1 into two sequences of unipolar pulses of positive and negative units. The secondary signal of these sequences, obtained from the output of the element OR 2, is used to reset the counter 11 and adjust the phase and frequency of the self-oscillating clock generator of the FALCH circuit, which increases the clock frequency in the separator 3. The same signal, inverted by the HE 4 element, serves to synchronize the trigger 5, which, together with the elements AND 8, 9, performs, respectively, counting and switching the pulses of the input signals so that the output of the OR element 12 is a signal of a single pair violation meter order of alternation of units representing pulses on P (consecutive positive or negative units of the input

signal. Similarly, the trigger 14 and the AND 15, 16 elements operate, and the output of the OR element 17 is a double violation signal of the alternating order parameter, which is n, -2 pulses per n consecutive positive or negative input signal units.

The clock pulses generated by the shaper 10 are fed to the synchronization inputs of 11 1 and registers 6, 7 and counter 11, at the output of which a PD-3 pulse appears at n consecutive zeros at its fault input and, accordingly, at the input signal of the device, which indicates a violation of the parameter the number of consecutive zeros.

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Registers 6 and 7 perform the function of normalizing the input sequences of positive and negative units with respect to clock pulses and shifting the normalized sequences by one clock cycle. Elements 19, 20 compare the signals of the first and second bits of registers 6, 7 and generate an error pulse when positive or negative units appear, the pulse duration of which exceeds one clock interval, which indicates a violation of the parameter minimum distance between two consecutive units of the same character. The OR elements 17, 18 carry out a logical addition of the parameter error impulses, the maximum allowable number of consecutive zeros, the order of the sequence of units, the minimum distance between two consecutive units of the same character of the quasi-Troich codes HDB3, CHDB3, AHDB3 and the order of unit alternation , the minimum distance between two consecutive units of the same sign of the algorithm of the quasitroic code of the PRF (AM1), respectively, and the elements And 21 carry out a proportional conversion of the duration of the total imp There are errors in the number of pulses, which eliminates the effect of their temporary overlapping when packaging them. communication channel and heatsink functionality of the device.

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Claims (2)

Claims this second entrances of the seventh and eighth elements are connected to the output of form1, a device for controlling a clock pulse maker, and fidelity of information transfer is quasi-inputs of the fourth element OR by a connecting code according to aut. St. No. 1177921, 5 yen, respectively, with the outputs of the second, characterized by the fact that, the first element OR, the fifth and the sixth, in order to increase the accuracy of control of the elements I. in the communication channels with packaging errors, introduced the seventh element And 2. The device according to claim 1, which is the first input of which is connected to the output-tO, which is defined as the third element OR, and the subsequent clock frequency is made in the form of a fourth-generation generator with phase-locking ment OR the eighth element AND, At frequency.