SU750479A1 - Terniary code encoder - Google Patents

Description

The invention relates to computing and can be used in the construction of discrete information processing systems. The ternary encoder is known, which contains a clock pulse generator, an AND element, an inverter, a start interval counter, an input pulse counter control trigger, an input pulse counter in the variable interval counter, and a variable interval counter ij. The disadvantage of this encoder is its low reliability. The closest technical solution to this invention is the encoder of the ternary code 1, O, 1, which contains ternary logic elements with four inputs and one output, with the fourth input of the encoder connected to the first input of the first ternary logic element, second, third, fifth and the sixth inputs of the encoder I are connected respectively to the first, second, third and fourth inputs of the second ternary logic element; the first and eighth inputs of the encoder are connected respectively to the first and fourth inputs of the third ternary logic element 2.. The well-known encoder of the ternary code has a complex implementation, i.e. it contains fifteen three-way logic elements. The purpose of the invention is to simplify the known encoder. This goal is achieved by the fact that the seventh input of the encoder is connected to the second input of the first and fourth input of the fourth ternary logical apements, the second and fifth inputs of the encoder are connected respectively to the third and fourth inputs of the first threefold logical element, the outputs of the first and second ternary logical elements are connected respectively with the second and third inputs of the third and fourth ternary logic elements. 7504 Fir. 1 shows a block diagram of an encoder; 2 is a faa-pulse diagram of its operation. The proposed encoder ternary code 1, O, 1 contains four ternary

Table 1 9 logical elements 1-4 with four inputs and one output, each of which performs triple logical operations described by a table, 1.

ABOUT

about ± 1

1 o

ABOUT

ABOUT

about o +1

+1

ABOUT

about

 .

ABOUT

± 1 +1 o o ± 1 o

+1

about

+1

± 1

± 1 o

ABOUT

about

ABOUT

± 1

+1

+1 o

+1

+1

± 1

± 1

about

+1

± 1

about

Htl

+1 +1

+1

These operations form a functionally complete system of logical functions.

The first input of the encoder X is connected to the first input of the ternary logic alias 3, The second input of the encoder Xa is connected to the third input of the first (1) and to the first input of the second (2) ternary logical epithets. The third input of the encoder X "is connected to the second input of the ternary logic element 2. The fourth input of the encoder X is connected to the first inputs of the first 1 and fourth 4 ternary logic elements. The L input of the encoder X is connected to the fourth input of Terminal 1 and to the third input of the second 2 ternary logical zdemeits. The sixth century. Xg encoder input is connected to the fourth input by trio

+ 1 + 1

-1 -1 +1

about

Bh, 1. -one

about

Vh. 2-g

(-)

out oh 3 +

BX.4 (-

about

f-)

+1 +1

one

- one

-1 about 1

it is a logical element 2. The seventh input of the encoder Hu is connected to the second input of the first 1 and to the fourth input of the fourth 4 ternary logic elements. The eighth input of the encoder X g is connected to the fourth input of the ternary logic element 3. The output of element 1 is connected to the second and third inputs of element 3, and the output of element 2 is connected to the third and fourth inputs

element 4.

The proposed encoder works as follows.

Claims (2)

A positive polarity signal is sent to one of the inputs of the encoder X-X, and at the output buses F and p} of the encoder (at the outputs of elements 3 and 4) code combinations appear in ternary form (bus 1 with a natural weight of 3 bus -. 3), but corresponding to the input bus. The clock power supply system of the Schratora circuit is three-phase; in this case, the positive signal to one of the inputs X - X g of elements 1-4 enters through three phases (one clock cycle) of information transfer by the circuit elements (Fig. 2). The second-phase clock pulse counts the information from elements 1 and 2 of the third phase - from elements 3 and 4. Pulses arrive at one of the inputs X - XQ of elements 1-4 during the same phase of the first phase. The encoder converts a signal with one - Chl into a signal at the outputs of inputs X. A and 2. meaning the number of the corresponding input encoded in the ternary code according to Table 2, Table 2. The first pulse of the first phase of a clock cycle according to the logic of the element written in Table 1, a positive signal from input X of the encoder is transmitted to the first input of element 3; the third phase pulse is a positive signal from the output bus p. (from element 3) exits the encoder to form the output combination (O1) corresponding to the input signal. Similarly, in accordance with FIG. 1, fig. 2 and Table 2, the signal is converted at the subsequent inputs, while at outputs p and F the code 1 corresponds to a positive polarity, and code I corresponds to a negative polarity signal. Using the proposed three-way encoder 1, O, 1 provides Compared with the known technical solutions, the following advantages: a) simplification of the encoder; b) increase the speed of the encoder; C) improving the reliability of the encoder. Claims of the Tertiary Code Encoder 1, O, 1, containing ternary logic elements with four inputs and one output, the fourth input of the encoder connected to the first input of the first three-dimensional logic element, the second, third, fifth and sixth inputs of the encoder are connected respectively to the first, the second, third and fourth inputs of the second ternary logic element, the first and eighth inputs of the encoder are connected respectively to the first and fourth inputs of the third and ternary logic element, characterized in that To simplify the encoder, the seventh input of the encoder is connected to the second input of the first and the fourth input of the fourth ternary logic elements, the second and fifth inputs of the encoder are connected respectively to the third and fourth inputs of the first ternary logic element, the outputs of the first and second threefold logical elements are connected respectively to the second and the third inputs of the third and fourth ternary logic elements. Sources of information taken into account during the examination 1. USSR author's certificate 443381, cl. Q 06 R 5/04, 1974. 2.Sokolov T.N., Vasilyev F.A. Ferrite logic elements and nodes of information systems. L., 197О,. 185 (prototype).