SU1443165A1 - Triple-state disjunction element - Google Patents

Abstract

The invention relates to a pulse technique and can be used in the design of logical nodes of information: ion systems on ternary logic elements with pulse inputs and outputs. The purpose of the invention is to simplify the device. Device co; holds the first and second ternary elements I and 2, the first and second input buses 3 and 4 and the output bus 5. In order to achieve the goal delivered, one inter-element communication is excluded. 2 ill., 2 tab.

Description

The invention relates to a pulse technique and can be used in the design of logical nodes of information systems on ternary logic elements with pulse inputs and outputs.

The aim of the invention is to simplify the device.

The goal is achieved by eliminating one inter-element communication.

Figure 1 presents the scheme of the three-digit element of disjunction; Fig. 2 shows timing diagrams for the operation of a three-digit disjunction element with conventional symbols.

The three-digit disjunction element contains the first and second ternary elements 1 and 2, the first and second input tires 3 and 4, and the output pin 5.

The input bus 3 is connected to the first negative subtractive input of the ternary element 1 and connected to the first positive summing input of the ternary element 2, the input bus 4 is connected to the second negative subtractive input of the ternary element 1 and to the second positive summing input of the threefold element 2, the input of the threefold element 1 is connected with the first, second negative subtractive inputs of the ternary element 2, the output of which is connected to the output bus 5.

In Figure 2, the following symbols are accepted: 6-8 — clock pulses of the first third phases; 9 and 10 - impulses on tires 3 and 4; P and 12 - write and read pulses from elements and 2.

The device's clock power supply system is three-phase, with the input signal combination to buses 3 and 4 through three phases (one clock) during the first-phase clock pulse. The clock pulse of the second phase is taken up from the information of the element 1, and the third phase from the element 2.

The ternary elements perform logical operations according to Table 1.

Three-digit information from tires 3 and 4 is converted to information on the three-digit element 2 (bus 5) according to Table 2.

The operation of the three-stage disjunction skeleton in accordance with the input combination (+1.0) is carried out

as follows (.first stroke in figure 2).

The first pulse of the first clock cycle according to the operation logic of the element recorded in Table 1, the positive pulse from the input bus 3 is transmitted to the first input of element 2, the third phase clock pulse at the output of element 2 is a positive pulse that arrives on the bus 5 .

Similarly, in accordance with figures 1 and 2 and table 2, the conversion of subsequent input combinations.

Claims (1)

Invention Formula A three-digit disjunction element containing two ternary elements, the first and second input and output buses, the first input bus is connected to the first negative subtractive input of the first and a positive summing input of the second ternary element, the second input bus is connected to the second negative subtracting input of the first and positive summing input the second ternary elements, characterized in that, for the purpose of simplification, the code of the first ternary element is connected to the first, second negative subtractive inputs of the second three ternary element, the output of which is connected to the output bus. Table 1 -TL clock input +1 -f- ZLGShP - /  counting banig oh jl reading with chitnbani -1 pu, g. 2