SU1531226A1 - Device for conversion of codes - Google Patents

Abstract

The invention relates to digital computing and can be used to build code converters in automated monitoring and control systems. The purpose of the invention is to increase the reliability of the device due to the introduction of a synchronization scheme for the operation of a pulse generator from control signals "More", "Less". To do this, the device includes the element OR 7, the D-flip-flop 8 and the element And 9, the output of which is connected to the clock inputs of the input 4 and output 3 codes. The first input element And 9 is connected to the output of the D-flip-flop 8, the clock input of which is connected to the output of the pulse generator 6 and the second input of the element And 9. The information input of the D-flip-flop 8 is connected to the output of the element OR 7, the first and second inputs of which are connected respectively to With the "More" and "Less" outputs of the compare unit 5. 1 Il.

Description

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The invention relates to digital computing and can be used to build code converters in automated monitoring and control systems. The purpose of the invention is to increase the reliability of the device.

The drawing shows a block diagram of a device for converting codes.

The code conversion device includes an input register 1, a conversion law selection block 2, an output code counter 3, an input code counter 4, a comparison block 5, a clock pulse generator 6, a PID 7, a D-flip-flop 8, an AND 9.

The device works as follows.

Commands that determine the input and output codes, and Zap1 commands: to the generator of 6 clock pulses are received from the communication channel through the input register 1 to the block 2 for the selection of the conversion law. The signs of the codes from the outputs of block 2 set the counters 3 and 4 to the zero state and the counter 3 of the output code to work in the output code, and the counter 4 and block 5 to compare the work to the input code. Comparison unit 5, the first information input of which receives the input code combination, and the information input — the code combination of the input. The combination of the counter 4 (to the beginning;:, I moment is zero) produces a signal. Above, which goes to the first input of the element OR 7, from the output of which it goes to the information input of the D-flip-flop 8.

With the arrival of the leading edge of the pulse from the generator 6, the output of the D-flip-flop establishes a signal arriving at the first input of the AND 9 element and allowing the pulses from the generator 6 to pass through the AND 9 element to the counting inputs of counters 3 and 4. Counters 3 and 4 depend on control The input signal from the comparison block 5, More or Less, works respectively for addition or subtraction. When the input code combination and the code combination of counter 4 coincide, the equal signal is output at the output of the comparison block 5 and the More signal is removed from the first input

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element OR 7. But at the output of D-flip-flop 8, this signal is removed only after the arrival of the leading edge of the pulse at the clock input of the D-flip-flop 8 from the generator 6. Removing the enable signal at the output of the D-trigger 8 prohibits the passage of pulses through element 9 and 9 the closure of the clock pulses to counters 3 and 4 is stopped, and from the counter 3 when the signal appears Equal to the code combination is removed, which is the converted code combination.

Claims (1)

Invention Formula A device for converting codes, containing an input register, whose input is the input of the device, and the information and control outputs are connected respectively to the information inputs of the first group of the comparison unit and the inputs of the conversion law selection block, pulse generator, input code counter and output code counter, outputs which are the outputs of the device, and the control inputs are connected to the outputs of the first group of the conversion law selection block, the outputs of the second group of which are connected to the control inputs The input code counter, the output of which is connected to the information inputs of the second group of the cf block, the More and Less outputs which are connected to the addition and subtraction inputs of the input and output code counters, and the Output Equal to the output input of the output of the output code, characterized in that, in order to increase reliability, an element OR, a D-trigger and an AND element are entered into it, the output of the AND element is connected to the clock inputs of input and output code counters, the first input of the AND element is connected to the output of the D-trigger, tact The primary input of which is connected to the output of the pulse generator and the second input of the AND element, and the information input of the D-flip-flop is connected to the output of the OR element, the first and second inputs of which are connected respectively to the outputs, More and Less, than the comparison unit.