SU1285489A1 - Averaging device - Google Patents

Abstract

The invention relates to devices for filtering and averaging electrical signals and can be used in automation systems and information measuring equipment. The aim of the invention is to improve the noise immunity of the device. The averaging device contains an integrating amplifier 1, a memory block 2 and a repeater 3 connected in series. Introduction to the device of the modulator 4, the polarity control unit 7 of the output pulses of the modulator, the reference time interval setting unit 6 and the comparator 5, as well as the corresponding connections, made it possible to increase the noise immunity of the device not only with exact equality of the period of interference to some fixed value, deviation of the period of interference from this value. 1 hp f-ly, 4 ill.

Description

1

The invention relates to a device for filtering and averaging electrical signals and can be used in automation systems and information measuring equipment.

The purpose of the invention is to increase the noise immunity of the device.

FIG. Figure 1 shows the functional diagram of the averaging device; in fig. 2 is a block diagram of a reference interval setting block; in fig. 3 is a diagram of the polarity control unit of the modulator output pulses; in fig. 4 shows timing diagrams for the operation of the device.

The averaging device (Fig. 1) contains an integrating amplifier 1, a memory memory 2, a repeater 3, a modulator 4, a comparator 5, a reference time setting unit 6, a modulator output pulse control unit 7, a pulse generator 8, a key 9, coupling capacitor 10. Modulator 4, integrating amplifier 1, unit

2 and tee repeater 3 are connected in series. Output repeater

3, switch 9 is connected to the information input of the integrating amplifier 1 and is the output of the device. The information input of the device is connected to the input of the modulator 4 and through a coupling capacitor 10 to the input of the comparator 5. The output of the latter is connected to the installation inputs of the polarity control unit 7 of the modulator output pulses and the reference time setting unit 6 whose clock inputs are connected to the generator output 8 pulses, a group of inputs of block 7 is connected to a group of outputs of block 6. Accordingly, the output of block 7 is connected to the control input of the modulator 4. The first and second outputs of block 6 are connected to the control input Apis unit 2 and memory control input key 9.

The reference interval setting unit 6 (FIG. 2) contains a positive pulse front driver 11, a negative ipulse driver 12, an OR-NO 13 element, an RS flip-flop 14, an AND-15 element, a 16 reference time generator. The installation and clock inputs of the unit for setting the reference time interval are connected to the first and

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the second inputs of the positive 11 and negative 12 pulse fronts, respectively, the output of the positive 11 pulse front shaper and the second output of the negative pulse front shaper 12 are connected to the corresponding inputs of the OR-NOT element 13. The output of the OR-NOT 13 element is also connected to the S-input RS -trigger 14, the R-input of which is connected to the output of the imager 16 of the reference time interval, the input of which is connected to the output of the NAND 15 element. Direct output 5 of the RS flip-flop 1-4 is connected to the first input of the NAND 15 element, sec Its input is the clock input of block 6.

The shaper 11 of the positive 0 pulse front consists of two RS-flip-flops 17. The shaper 12 of the negative edge of the pulse consists of the HE 18 element and two RS-flip-flops 19. The shaper 16 of the reference time interval contains counters 20 and the AND-NE 21 element.

The polarity control unit 7 of the modulator output pulses (Fig. 3) contains a frequency divider 22, a forward count pulse generator 23, a reverse count pulse generator 24, two reversible counters 25 and 26, an And 27 element, an RS flip-flop 28.

5 The frequency divider 22 is performed on the RS-trigger 29, the pulse formers of the forward 23 and reverse 24 counts contain the elements AND-NOT 30 and 31. The reversible counters 25 and 26 0 are executed on the counters 32 and 33, respectively. The input of the frequency divider 22 is the clock input of the block 7, the first inputs of the forward pulse formers 23 and the reverse of the 5th and 24 counts are the installation input of the block 7.

The output of the frequency divider 22 is connected to the first input of the driver

0 23 direct counting pulses, the first and second outputs of which are connected to the first inputs of reversible counters 25 and 26, respectively. The first and second outputs of the 5 liter 24 counting pulses are connected to the second inputs of the reversing counters 25 and 26, the outputs of which are connected to the corresponding inputs of the And 27 element. to one of the inputs of the counting pulse generator 23, and is the code of block 7.

The device works as follows.

At time, the signal U

t About (Fig. 4)

6X

and + and

sin

),

P

where and

- voltage to be measured;

and - amplitude of interference;

T - period of interference. The period of operation of the device is equal to the period of interference T. Each period of operation of the device consists of four cycles. The variable component of the input signal is fed through the coupling capacitor 10 to the comparator 5. In the first half-period of operation of the device with a positive interference signal at the output of the comparator 5 there is a signal of a logical unit. At time t, the voltage of a logical unit appears at the output of the control unit and at the first output of the unit 6 of the reference time interval setting. The modulator 4 is switched to the inversion mode and the key 9 is JJK. At the second output of the reference time setting unit 6, a short-time signal appears with the signal, and in memory block 2, the value of the initial state of the integrating amplifier 1 Uj, 9 is closed for a time h. At the output of block 7, the voltage of the logical unit must be present for a time of 1 /

(h + h), starting from the moment of equality of the signal of the interference to zero, where h and h, respectively, are half-periods of the original and real. In the first beat, the value of H is not known at the output of the block. 7, the voltage of the logical unit is present over time h ,. By the end of the first clock cycle t, t, + h, the voltage on the integrated mode amplifier 1 reaches the value U t, l:

UHW - -r (-u ,,) dt

 t

-Ubltcl- Gui „It, - At,

 -t where t, and T, j are constant times

integrating

input signal and feedback signal respectively.

Choose

 2h T

get

UHtt: J + N.shg () b „)

iO

-G

u.l

U u cjl u,

where tO is the cyclic frequency of interference. In the second cycle of operation, the key 9 is open, the modulator 4 does not invert the input signal and by the time tj h the voltage on the integrating amplifier 1 reaches the value and t

f45

Ctjl U,

and

(,,

. cOt

cosui h

U u cjl u,

in the third cycle, the modulator 4 inverts the input signal during the time i 1/2 (he + h). The switch 9 closes the control signal of the logical unit from the fifth output of the block 6 for setting the reference time interval for time h. I integrate voltage (than I-f / 2

le 1 at time t (h + h) reaches

(t -.)

U u cjl u,

+ (COS-J blbo cosu) h-1).

In the fourth cycle, the signals at the output of block 7 and at the first output of the block b of the reference time interval are absent. The input of the integrating amplifier 1 posyvaet non-inverted input signal. At the end of the fourth cycle, by the time t 2h, the voltage on the integrating amplifier 1 reaches

Untt

, u, Lt,: i

U.

and

,(one - - )

(cos uJh + sin J

b) 2 h

In the second period of operation of the device, the modulator 4 inverts the signal to be converted in time 1/2 (HO + h). Key 9 is closed at the time of controlling a yuatsin signal with a per5

the first output of the block 6. At the beginning of the second period, the control signal from the second output of the block 6 briefly closes the key of the memory block 2, in which the value of the voltage of the integrating amplifier 1 is memorized.

  t

 four

. -1- (h

-t- h) voltage

on the integrating amplifier 1, it reaches the value U t,:

  .Vk

and t, tj - J-Ju ltjdt

n -S-l Ltl- | - (4-f and

 ,

-2-U,

(h.ih) +

I

- | -U, Lt.l -. (Usinu) b | -).

The second cycle of operation at the input of the integrating amplifier 1 receives a non-inverted input signal. Key 9 is open. To the moment

of time

 6

t / + h voltage

on integrated electronics, amplifier 1 becomes and t,.:

And b,

and, Ct, - {- g u ,, c3t

U u

- u.rtj + - and

+ .2sinu3

(d1 I.

The operation of the device in the third cycle is identical to the operation in the first cycle.

and by the time t- t + t

to (h + h) on the integrating amplifier 1, the voltage reaches the value U.tt:

u, ct, uat, i- ujtjdt

. -1- f

 H.

U, (h,

and dt

 h + ho4 1 + -) Ut

uit

h.)

2

(-1 + sinu3

In the fourth cycle, the device operates in the same way as in the second one. By the end of the second period of operation t g 4h, on the integrating amplifier 1, the voltage reaches.

u.Lt, ujt, --1- i,; dt. . 4- and

Further, the device operates as during the second period of interference, reaching the end of the K-th period of the value Uj, k Tn}:

 - Jk-Tj -2j} and ,.

At 2h

- one

Ujk tj and.

From the above expressions for the output voltage of the device, it follows that the last

does not depend on the voltage of the interference, not only with the exact equality of the period of interference to some fixed value, as was the case in the prototype, but also when the period deviates

interference from this value, i.e. The proposed device possesses noise immunity to interference with a slowly varying frequency. As an example of such interference, you can specify a network interference with a frequency of 1 / T 50 (1 + + 0.02) Hz. The value of T is chosen from the ratio T T

where, - the maximum value of the period of interference.

.

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Claims (2)

1. Averaging device containing series-connected 0 an integrating amplifier, a memory unit and a repeater, the output of which is an output of a device, characterized in that, in order to improve noise immunity, a modulator, a separation capacitor, a polarizer control unit of the output pulses of the modulator, a reference interval setting unit are inserted into it time pulse generator comparator and 40 key connected between the first information input of the integrating amplifier and the output of the repeater, the second the information input of the integrating amplifier is connected via a modulator 45 to the information input of the device, connected via a coupling capacitor to the first input of the comparator, the second input of which is connected to the zero potential bus, and the output 50 is connected to the installation inputs of the polarity control unit of the output pulses of the modulator and the reference time reference block which are connected to "By the output of the pulse generator, the control input of the modulator is connected to the output of the polarity control unit of the output pulses of the modulator, the input group of which is connected to the output group of the biocodes of the reference time interval, the control input of the key and the recording control input of the memory block are connected to the first and second outputs of the reference interval setting unit, respectively, with the polarity control unit of the modulator output pulses comprising a frequency divider, a direct counting driver, and a reverse pulse pulse, two reversible counters, an And element and an RS flip-flop, the output of the frequency divider connected to the clock input of the direct count pulse generator, the first and second outputs of which are connected to the summing inputs of the first and second reversible counters, respectively, whose readout inputs are connected with the first and second outputs of the counting pulse generator, and their outputs are connected to the first and second inputs of the And element, the output of which is connected to the R input of the RS flip-flop, the installation inputs of the the forward and reverse count pulse generators are the installation input of the polarity control module of the modulator output pulses, the frequency divider input and the clock input of the counting pulse generator are the clock input of the modulator output pulse polarizer, and the information inputs of the forward and backward pulse formers the counting down and the S input of the RS flip-flop form a group of inputs of the polarity control unit of the output pulses of the modulator. 2. The device according to claim 1, wherein the unit for setting the reference time interval contains shapers of positive and negative pulse fronts, the OR — NO element, the RS flip-flop, the NAND element and the shaper of the reference time interval, and The first and second inputs of the positive and negative pulse fronts are the installation and clock inputs of the reference interval setting block, the output of the pulse, the positive pulse front bodies, and the first output of the negative edge of the pulse shaper. A is connected to the corresponding inputs of the OR-NOT element, the output of which is connected to the S-input of the RS-flip-flop, which is connected to the output of the driver for the reference time interval, and the direct output through the AND-NOT element is connected to the input of the reference time sensor the positive edge pulse driver output is the first output of the block, the second pulse negative edge driver output is the second block input, the inverse output of the RS flip-flop, the output of the OR-NOT element and the direct output of the RS flip-flop are grouped block outputs. /, / z p P pC / Sh 1SHI / M M / J, / / Iljh / L // 7 / L et) / WOO ( H dlonu9 / five rc / J9 L-1 D / yy V  Tg hU4Jl & i I HI a R a Qcifttoivj fl f "one  eleven "3 M NP P f CLL o Csj I J ib .- P gg . fl f "one