GB2246687A - Receivers for data transmission systems - Google Patents

Abstract

A receiver, for use in data transmission systems in which encoded digital data signals DS subject to noise or interference are transmitted over a data transmission path at a particular data rate or frequency, comprises a binary counter DC to which incoming data elements of logic "1" and/or logic "0" are applied to cause the counter to perform an UP and/or DOWN counting operation from an initial rest position for the duration of each data element in turn. The counting rate is predetermined by the output frequency of an associated oscillator OSC and is relatively high compared to the data rate. The most significant bit of the final count position of the counter at the end of each received data element represents the best estimate of the binary logic value of that data element. The final count is also a measure of the quality of the received data. <IMAGE>

Description

IMPROVEMENTS RELATING TO DATA TRANSMISSION SYSTEMS The present invention relates to data transmission systems of the kind in which encoded digital data signals are transmitted over a data transmission path at a particular data rate or frequency.

In data transmission systems of the above kind the transmitted digital data may be corrupted by electrical noise or interference (e.g.

radio frequency interference) to which the digital signals are subjected during transmission. As a consequence of such corruption the system receiver may falsely interpret the true logic values (i.e.

"0" and "1") of data elements in a digital data stream. This problem of false interpretation of received data may at least be alleviated by the use of analogue integration techniques in respect of each of the data elements received. however, such analogue integration techniques can be difficult to incorporate in purely digital circuitry or gate arrays.

The present invention therefore provides for use in a digital data transmission system of the kind described a data receiver comprising a binary counter to which incoming data elements of logic "0" and /or "1" are applied to cause the counter to perform an up and/or down counting operation from an initial reset position for the duration of each data element in turn, the counting rate of the counter being predetermined by the output frequency of an associated oscillator which is relatively high compared to the data rate, in which the most significant bit of the final count position of the counter at the end of each received data element represents the binary logic value of that element.

In carrying out the present invention the most significant bit of each of the final count positions of the counter may be latched into a latching circuit in response to a data or timing clock pulse applied thereto.

The binary significance of the most significant bit of each final count position is the inversion of the logic value of the data element.

The count position of the counter at the end of each incoming data element is indicative of the quality of the data element and may be stored for signal processing purposes.

By way of example the present invention will now be described with reference to the accompanying drawings in which: Figure 1 shows a block schematic diagram of a digital data receiver according to the present invention; Figures 2(a) and (b) illustrate the corruption of digital data elements that can take place due to electrical noise etc.; Figure 3 shows the waveform diagrams of signals occurring at various points in the data receiver of Figure 1; and, Figures 4 and 5 show diagrams illustrating the digital counting operation (including counter tables) by the receiver of Figure 1 in respect of correct and erroneous data, respectively.

Referring to Figures 1 and 2 of the drawings, Figure 1 shows a block diagram of a data receiver for recovering encoded digital data transmitted from a remote transmitter over a transmission path. The received digital data is applied to a digital binary counter DC of the receiver. The digital data received will comprise a stream of data elements having binary logic "1" and/or logic "0" values with the specific binary logic values being effectively represented by voltages transmitted over the transmission path. An example of such digital data is shown in Figure 2(a). However, during transmission of these data elements the elements may be corrupted by being subjected to electrical noise and/or interference (e.g. radio frequency interference) as indicated in Figure 2(b) so that the data signals actually received by the receiver of Figure 1 may be seriously distorted.

As will be appreciated, for the recovery of the encoded data in the receiver clocking pulses may be generated at the receiver and synchronised with the data rate or frequency of the transmitted data by means of a phase lock loop arrangement (not shown). These clocking pulses may be utilised for the effective interrogation of incoming data elements to interpret the logic values of data elements.

However, as will be seen from Figure 2(b) if such interrogation of the corrupted data elements were made at single interrogation clocking points in each data element then an incorrect logic value could easily be assigned to the data element in question.

With a view to avoiding such incorrect interpretation of the logic values of distorted data elements the receiver of Figure 1 recovers the data by a digital equivalent of the data element integration techniques previously referred to. The technique involved in the present embodiment also provides an indication of the quality or confidence level of each data element recovered.

Reverting to Figure 1, the digital counter DC as well as receiving the incoming stream of data elements also receives the output from an oscillator OSC which may comprise a standard oscillator circuit providing a digital signal OS which as can be seen in Figure 3 has a relatively high frequency compared to the frequency or data rate of the incoming data signals DS.

The data clock or data timing pulses DT (Figure 3) referred to previously and having the same frequency as the data rate of the incoming data are applied to a pulse generator PG which may comprise a standard monostable circuit producing a narrow pulse PS.

at each of the positive-going edges of the data clocking or timing signal DT. The output signal PS is applied to the reset input of the counter DC. This counter DC is a digital binary counter circuit having a direction of count controlled by an UP/DOWN digital input receiving the incoming stream of data elements.

The counter will be reset to binary condition 0000.

Consequently, if the data input to the counter has a logic value 1 then the counter will count up one binary digit for each clock cycle input as follows: MSB RESET 0000 CLOCK 0001 CLOCK2 0010 CLOCK3 0011 and so on.

If the UP/DOWN input is a binary "0" the counter will similarly count down as follows: MSB RESET 0000 CLOCK 1111 CL0CK2 1110 CLOCK3 1101 and so on.

As can be appreciated from the two tables shown for UP and DOWN counts the most significant bit (MSB) of the count will not change until the count reaches the halfway point.

For the purpose of data recovery the magnitude of each count is preselected so that it is greater than twice the number of clock cycles occurring during each data element. Purely by way of example, with a data rate of 1 Kilobit/second and an oscillator frequency of 25KHz 25 clock cycles or counts per data bit would be provided. The binary counter would therefore need to count at least 50 (i.e. twice the number of clock cycles per data bit). This would necessitate the use of a 6 bit binary counter giving a maximum count of 64. In actual practice the oscillator frequency/data frequency ratio would be significantly higher.

In operation of the receiver the pulses from the pulse generator PG reset the counter DC to its 0000 condition. The incoming data applied to the UP/DOWN input of the counter DC causes the counter to begin counting UP or DOWN in dependence upon the logic value of the data element input. At the end of the count made in respect of each data element the significance of the most significant bit of the count will represent the best estimate of the logic value of the data element concerned.

Referring to Figure 4 which illustrates the counting operation by the counter DC both diagramatically and in tabular form it will be seen that the most significant bit at the end of the logic "1" data element DA is binary "0" which in the present embodiment by the adoption of an inverted representation represents a logic "1" data element whereas at the end of the logic "0" data element DB the most significant bit is binary "1" representing a logic "0" data element.

As each element is recovered the significance of the most significant bit of the end count is applied to a latching circuit LA in which the most significant bit is latched by a data clocking or timing pulse DT.

A counter reset pulse is then generated by the pulse generator PG and the counter DC is reset for recovering the next data element of the incoming data stream.

As can be seen from Figure 5 of the drawings a recovery of data elements is correct in respect of the data elements DA' and DB' in spite of the fact that errors occur in the data element waveforms due to noise or interference corruption. This is because the most significant bit of the counts at the end of the data elements DA' and DB' are still "0" and "1", respectively, as in the case of Figure 4.

From the count diagrams in Figures 4 and 5 it will be appreciated that the final count of the UP/DOWN counter DC is a measure of the quality of the received data, a high positive and/or high negative count represented by the lengths of the lines a and b indicating the degree of cleanness of the incoming data. This information could also be stored and utilised in subsequent data processing circuits.

It may here be mentioned that the recovery of data could be improved by increasing the oscillator frequency thereby providing more data samples but this in turn would require an increase in the length of count of the counter DC.

Claims (7)

1. For use in a digital data transmission system of the kind hereinbefore described, a receiver comprising a binary counter to which incoming data elements of logic "1" and/or "0" are applied to cause the counter to perform an UP and/or DOWN counting operation from an initial reset position for the duration of each data element in turn, the counting rate being predetermined by the output frequency of an associated oscillator and relatively high compared to the data rate, in which the most significant bit of the final count position of the counter at the end of each received data element represents the binary logic value of that data element.

2. A receiver as claimed in claim 1, in which the most significant bit of each final count position of the counter is latched into a latching circuit in response to a data or timing clock pulse applied thereto.

3. A receiver as claimed in claim 1 or claim 2, in which the binary significance of the most significant bit of each final count position is the inversion of the logic value of the data element.

4. A receiver as claimed in any preceding claim, in which the length of each count by the counter during reception of a data element is greater than twice the number of oscillator signal cycles occurring during each data element.

5. A receiver as claimed in any preceding claim, in which the final count position of the counter of the end of each incoming data element is indicative of the quality of the data element and is stored for subsequent signal processing purposes.

6. A data transmission system including a receiver as claimed in any preceding claim.

7. A data receiver substantially as hereinbefore described with reference to the accompanying drawings.