SU377781A1 - DECODER - Google Patents

Description

one

The invention relates to computer technology, communications technology and telecontrol, where the task of noise-resistant transmission of information.

A self-decoding device containing a binary signal receiver connected to a registration circuit and an error detection circuit, in which the redundancy of group codes is used to increase the reliability of the operation to detect errors. However, increasing the reliability of the received information, especially in systems with feedback, is achieved at the cost of reducing the capacity of the systems due to the retransmission of code combinations in which errors are detected.

In some cases, for transmitting large amounts of information over a channel with a relatively high relative level of interference, the capacity of the feedback system may be insufficient. If the requirements on the reliability of receiving this information are lower than the communication system can provide, then, in order to increase the capacity of the communication system, it is difficult to detect a large part of errors, it is advisable to correct some of the most probable errors. This will lead to a decrease in the number of inquiries and at the cost of some decrease in the reliability of the information being acquired, an increase in the capacity of the communication system will be achieved. By changing the proportion of corrected errors FROM the total number of possible errors, it is possible to regulate to a certain extent the system capacity and the reliability of the received and n forma tions.

The purpose of the invention is to increase the reliability of operation of the device by increasing the throughput of feedback systems when using codes with an even number of "units."

The goal is achieved by the fact that the proposed device introduced a reception scheme with zero

zone, two delay registers, two counters even, two AND circuits and an adder for module two, the output of the binary signal receiver is connected to the input of the receiving circuit with a zero zone, the output of which is connected to

the input of the first delay register and the input of the first parity counter, the output of the registration circuit is connected to the input of the second delay register and the input of the second parity counter, the outputs of both parity counters are connected to the inputs of the NI circuit, the output of which is connected to the first input of the second And, the second input of which is connected to the output of the first delay register, the outputs of the second delay register and the second circuit

"And connected to the inputs of a modulo-two adder, whose 1 OUTPUT is connected to the input of an error detection circuit. This allows to correct some of the errors, since, along with the usual registration of binary characters, signs whose value is doubtful are fixed (reception with a double zero zone) ..

If a parity check is performed in the received code combination, then regardless of the number of binary characters received in the zero zone, the code combination is applied to the error detection circuit without change. If, in the received code combination, the parity check is not performed and only one uncertain binary character is fixed at the same time, then it is inverted to the opposite value. If in the received parity code combination the parity check is not executed and at the same time an odd number of unstable binary bits are fixed, then these signs are inverted to the opposite value. In all other cases, the inversion of binary characters does not occur.

Thus, the correction of either parts of single or part of odd most probable errors occurs.

The drawing shows a block diagram of the proposed device. In the block diagram, the following notation is used:

1 - discrete channel output;

2- receiver of binary signals;

3- registration scheme

4- scheme with zero zone; five; 6- delay registers;

7; 8 - parity counters9 10 - schemes

And - adder modulo 2;

12 is an error detection circuit.

The decoding device operates as follows.

From the output / discrete communication channel, receiver 2 receives a sequence of binary signals, which, after conversion, are fed to circuits 3 and 4. The registration circuit 3 records the signals, and the reception circuit 4 with the zero Zone, with signal distortions exceeding a certain value, produces Z-signals of uncertain reception.

The binary signs from the output of the registration circuit 3 are fed to the delay register 5 and the parity counter 7. Z-signals from the output of circuit 4 are fed to the register 6 delay, and the counter 5 parity. The number of delay register cells is equal to the number of code pattern bits. The output of register 5 is connected to one input

adder 11, and the output of the register 6 che, cut the scheme "And 10 to another input of the adder. Counter 7 checks the parity code combination. Counter 8 is used to determine the number Z in the received code pattern. At the end of the reception of a code combination after polling, the counter 8 gives out a pulse, or only when, for the length of the code combination recorded, only one signal Z is given, or when

recorded an odd number of signals Z.

If, after polling, at the end of the reception of the code combination, the pulses are output from the outputs of both counters 7 and S, the AND 9 circuit opens the AND W circuit for the write-off time of this delayed combination from the register 5 to the first input of the adder 11. To the other input of the adder 11 through the scheme "And 10 received delayed Z-signals. Upon receipt of the Z-signal, the adder 11 inverts (corrects) the value of the binary sign.

If at the end of the reception of a code combination at least from one counter 7 or 8, a pulse is not output, then the And W pattern does not open and error correction is not performed.

Thus, using the described device in code combinations, the most probable errors are corrected. Decoder fixing power

The device can be adjusted by changing the width of the zero zone of the circuit 4.

Subject invention

A decoding device containing a binary signal receiver connected to a recording circuit and an error detection circuit, characterized in that, in order to increase the reliability of operation of the device, a reception circuit with a zero zone is introduced into it,

two delay registers, two parity counters, two circuits “And. and a modulator but two modules, with the output of the binary signal receiver connected to the input of the reception circuit with zero zone, the output of which is connected to the input of the first delay register and the input of the first parity counter, circuit output registration is connected to the input of the second delay register and to the input of the second parity counter, the outputs of both parity counters are connected

with the inputs of the first circuit "And, the output of which is connected to the first input of the second circuit" And, the second input of which is connected to the output of the first delay register, the outputs of the second delay register and the second circuit "And connected to the inputs of the modulo two, the output of which is connected to the circuit error detection.