SU1566488A1 - Majority binary code decoder - Google Patents

Abstract

The invention relates to computing and communication technology. Its use in digital information transmission systems makes it possible to increase the information content by reducing the redundancy of the decoded code. The decoder contains a ring register 2, a shaper 3 checks, a major element 4, a pulse counter 9, a memory element 13, AND elements 14-16 and an OR element 17. By introducing a serial code converter 1 in parallel, a synchronization unit 5, an element 6 EXCLUSIVE OR , delay elements 7.8, comparison block 10 with a threshold, buffer register 11 and trigger 12 in a decoder, decoding a code (N, K + 1) with less redundancy than the prototype code (N, K) is provided. 3 il.

Description

SP

O5 O5 4. 00

oo

The invention relates to computing and communication technology and can be used in digital information transmission systems.

The purpose of the invention is to increase the information content by reducing the redundancy of the decoded code.

Figure 1 shows the functional diagram of the decoder; figure 2 - block synchronization; figure 3 - timing charts.

Majority binary code decoder contains serial code to parallel converter 1, ring register 2, checker 3, majority element 4, synchronization unit 5, EXCLUSIVE OR 6, first 7 and second 8 delay elements, pulse counter 9, comparison unit 10 with threshold , buffer register 11, trigger 12, memory element 13, first 14, second 15 and third AND elements and OR 17.

The serial to parallel converter I is a shift register.

Shaper 3 checks is used to obtain check characters from the received word in accordance with the coding rules of the received code and is a block of d-1 modulo-two adders, where d is the number of code checks (n, k, 2t + 2), each of these adders has an even number

inputs 1

p-1 d-g

The synchronization unit 5 can be implemented (FIG. 2) on a resonant amplifier 18, a first limiting amplifier 19, a phase detector 20, a low-pass filter 21, a tunable frequency generator 22, a second limiting amplifier 23, a pulse counter 24, a decoder 25 and a differentiating element 26. Figure 2 shows the first 27 and second 28 outputs of block 5. Memory element 13 is a D-trigger.

On fig.Z marked the following signals: h - the sync signal f on the second output 28 of the block 5 synchronization; 5- clock sequence F at the first output 27 of the synchronization unit 5; 0 - code on all parallel outputs of the ring register 2; g is the code at the outputs of the imager 3 checks; "J.- clock sequence F on you

0

during the first delay element 7; e is the signal at the output of the first element And 14; - the number of clock pulses counted by the counter 9; j is information in buffer register 11; and a signal at the first and second outputs of the comparison unit 10 with the threshold; , - information in memory element 13; l is the code at the output of the element OR 17; © - modulo two summation; rj is an error symbol.

The decoder uses a code (n, k + 1, 2t + l), which should be transparent (n is the code length; k is the number of information symbols; 2t + l is the number of separated checks).

The majority binary decoder (n, k + 1, 2t + l) code works as follows.

The time diagram of the decoder operation is considered on the example of decoding the cyclic Hamming M code (7.4).

Accepted with speed

k-h

, double

five

0

five

0

five

the information is fed to the input of the converter I in serial form by the information bits ahead. Under the action of the clock frequency F, coming from the synchronization unit 5, the code word is advanced to the left. After the entire code word of length n characters is written to converter 1, from the synchronization unit 5 comes a clock signal φ corresponding to the boundary of the code word. This signal performs parallel rewriting of the code word from converter 1 to the ring register 2. To ensure reliable rewriting of the code word to register 2, synchronization unit 5 provides a delay of the clock sequence F relative to the clock signal f by the time required to reliably write the code word in parallel to register 2 Next, in the ring register 2, under the action of the clock sequence F, the received code word is cyclically shifted. In this case, the parallel outputs of register 2 sequentially appear cyclic shifts of the received code word, n-1 bits of register 2 are connected to the shaper 3, which ensures the formation of non-trivial checks. One rachv

five

trivial pro (i)

and excluded because does not contribute additional information about errors in the code word.

Shaper 3 checks completes modulo 2 of some of the n-1 bits of register 2 to get d-1 nontrivial split checks (for the case when the input M (n, k) code has a system of split checks). For code M (7.3), which is dual to the received code M (7.4), the system of separated checks is

+ a

3

a „a.

+ a.

art a + a.

Figure 3 presents in digital form the d-1 outputs of the imager 3 checks, formed in accordance with the system (2). The major element 4 on the d-1 inputs generates at its output a signal in the event that

if not less than

of d-1 checks are complete. In the proposed decoder, it is sufficient to perform 2 of the Zl checks. At the output of major element 4, the transmitted code word appears if the number of errors in the received code word

t

± 1 I 2 J

where x is the taking of the integer part in the direction of decreasing the number.

On fig.Z in the fifth cycle shows the correction of a single error. Since the alphabet M (n, k + l) of the code contains the alphabet M (n, k) of the code and its inverse alphabet, in the case of receiving a code word belonging to the inversion of the alphabet M (n, k) of the code, the output of the majority element 4 the code word inverse to the transmitted one (fig. 3, the second cycle for the case of no errors and the third cycle for the case of a single error).

the received code word from the register 2 output and the corrected code word from the output of the majority element 4 are fed to the two inputs of the SPACK element

5664886

THE SALMER OR 6 (adder mod 2). At its output, the level of logical I appears only in the case of a mismatch of signals at its inputs. The unit level from the output of element 6 allows passage through the element And 14 of the clock sequence F, delayed by the delay element 7 relative to the sequence F on

ten

15

20

25

time where 1Ev g

E E4

(five)

 E4

time delay shaper 3 checks; the delay time of the majority element 4 to the counting input of the counter 9.

Thus, the binary number recorded in counter 9 during the decoding time of one codeword is equal to the number of unmatched characters in the received and decoded codewords.

The binary number from counter 9 in parallel form enters block 10 in comparison with the threshold. In the case of using the code, only for correcting errors in the block 10 comparison with the threshold two thresholds are set.

P

 n - t;

(6)

where yes

4 s

t - correcting ability to

35

40

If the number in the counter 9 satisfies the expression

n NC4 9 7 „1Г,, (7)

the clock signal f passes from the input of block 10 to its first output and sets the trigger 12 in 1.

If the number in the counter 9 satisfies the expression

About Ј N

SC 9

Јt,

(eight)

the clock signal f passes from the input C. unit 10 on its second output and sets the trigger 12 in the O. For the code M (7.4)

0

n.

6;

- 0 + 1 - I. (9)

five

l - 1 - at 11 2

Simultaneously with the operation of the counter 9, the corrected code word is written into the buffer register 11 and the code word is promoted through it by clocking the register 11 with the clock sequence F1. After the clock pulse from the beginning of the code word, the first bit of the code word a0 has

with recorded in the last (most right) de register 11.

Further, the sync signal φ, passage through the block 10 in comparison with the threshold, sets trigger 12, depending on the fulfillment of conditions (7) or (8), to 1 or 0, respectively. Behind the clock signal F, the clock pulse F of the sequence F closest to it rewrites the state of the last register register 11 in memory element 13. Depending on which of the elements And 15 or 16 served a single

the potential from the outputs of the trigger 12, the direct or inverse signals from the outputs of the memory element 13 are passed to the output of the device through the elements 15 and 16 and OR 17.

Thus, if the transferred codeword belongs to the inverse alphabet M (n, k) of the code, at the output of the majority element 4 it appears corrected, but in the inverse form. In this case, if the condition (7) is fulfilled, the trigger 12 destroys the passage to the device output of the corrected code word from the inverse output of the element 13, which corresponds to the transmitted word.

In case of failure to comply with conditions (7) and (8), the decoder fails (Fig. 3, the fourth cycle of the occurrence of a two-fold error, exceeding the correcting ability of the M code (7.4).

The proposed decoder compared with the known provides a reduction of the unit redundancy of the decoded information and the corresponding higher

nizi and connected

n 5

0

five

AND elements and OR element, characterized in that, in order to increase the information content by reducing the redundancy of the decoded code, a buffer register, a trigger, an EXCLUSIVE OR element, delay elements, a comparison unit with a threshold, a synchronization unit and a serial-to-parallel code converter are entered into the decoder The information input of which is combined with the input of the synchronization block and is the input of the decoder, the first output of the sync block of the input of the first

the delay element and the push-in inputs of the memory element, the ring register and the sequential code converter in parallel, the output of which is connected to the installation inputs of the ring register, the serial output of which is connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the first input of the first element AND, the output which is connected to the counting input of the pulse counter, the second output of the synchronization unit is connected to the write enable input of the ring register, the so-called input of the comparison unit and the threshold input of the second delay element, the output of which is connected to the zeroing input of a pulse counter, which outputs are connected to data inputs of the comparator with a threshold, the first and second outputs which are respectively connected to the mounting Valid Valid and zeroing the trigger forward and inverse outputs kotorchego

The specific rate of the received in-, Q is connected to the first inputs of the correspondence. The relative gains in redundancy and speed are determined by the expressions

about - 5 ft G nk k

Claims (1)

Invention Formula A major binary code decoder containing a ring register, the parallel outputs of which are connected to the inputs of a test generator, the outputs of which are connected to the inputs of the majority element, a pulse counter, a memory element, 45 50 55 The second and third elements AND, the output of the first delay element is connected to the second input of the first element AND and the clock input of the buffer register, the output of the majority element is connected to the second input of the EXCLUSIVE OR element and the information input of the buffer register, the output of which is connected to the information input of the memory element, the inverse and direct outputs of which are connected to the second inputs of the second and third AND elements, respectively, the outputs of which are connected to the inputs of the OR element whose output is output g decoder. The second and third elements AND, the output of the first delay element is connected to the second input of the first element AND and the clock input of the buffer register, the output of the majority element is connected to the second input of the EXCLUSIVE OR element and the information input of the buffer register, the output of which is connected to the information input of the memory element, the inverse and direct outputs of which are connected to the second inputs of the second and third AND elements, respectively, the outputs of which are connected to the inputs of the OR element whose output is output g decoder. to l I 00 J O 1 1 100011001000110 JfflJB fflu Put 3 Editor I. Shulla Tehred M. Didyk Order 1229 Circulation 661 Subscription NIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk naGt., L. FIG. 2 Compiled by O. Reninska Proofreader M.Kucher va