SU372706A1 - DECADE RECORDING DEVICE - Google Patents

Description

The invention relates to a pulse technique.

Known decade counting device implemented on the transistor-transistor elements, containing triggers, as well as the input logic unit, made on the basis of the schemes “AND-NOT.

A disadvantage of this device is its limited functionality.

The purpose of the invention is to expand the functionality of the device, as well as to reduce external communications by using the phase-impulse presentation of information.

It is achieved by the fact that the proposed device contains an output driver made on the basis of the AND-NOT scheme, one of the inputs of which is connected to the counting input of the decade, and the remaining inputs are connected to the single outputs of the first and fourth triggers, the output of the AND-NOT connected to the output signal bus, the spike of the counting pulses through the inverter and the control pulse bus directly connected to the input of the "AND-NOT input logic unit, the output of which is connected to one of the inputs of the other" IS-NOT, second input oh connected to the clock bus, and the output - to the counting input of the decade.

FIG. 1 is given a functional diagram of the described device; in fig. 2, 3 - time diagrams of its work in various modes.

The device includes triggers 1–4 with a common input of the installation to “zero, connected to the bus 5 of the installation to“ zero through the inverter 6, input logic devices made on three circuits “AND-NE 7-9,

and the output circuit "AND-NOT 10 driver output signals. The output of the circuit "AND-NOT 7 is connected to the counting input of the trigger / and one of the inputs of the circuit" AND-NOT 10; one of the inputs of the circuit "AND-NOT 7 is connected to bus 11

synchronizing signals, the second input of the circuit “AND-HE 7 is connected to the output of the circuit“ AND-HE 8, one of the inputs of which is connected to the bus 12 of control signals, and the second one - with the output of the circuit “I-NE 9. The input of the circuit

“AND-NO 9 is connected to the bus 13 counting signals. The output 14 of the trigger 1 is connected to the counting inputs 15 and 16 of the trigger 2 and 4 and with one of the inputs of the circuit "AND NOT 10. The output 17 of the trigger 2 is connected to the counting input 18

trigger 3 and with the input 19 set to “zero of the trigger 4, the output 21 of the trigger 3 is connected to the similar input 20 of the trigger 4. The output 22 of the trigger 4 is connected to one of the inputs of the circuit AND 10, and its output 23 to the input

24 sets to zero trigger 2.

After signaling to bus 5, all the triggers are set to the zero state. The sequence of pulses (Fig. 2 a), not available on the bus //, through the "AND-NOT

7 acts on the counting input of the trigger / and then after recalculation by two (Fig. 2 b), it arrives at the counting input of the trigger 2, and then after recounting on four (Fig. 2 c) - to the input 18 of the trigger 3.

The trigger 4 is maintained in a zero logical state by signals from the outputs of the trigger 2 and 3, if at least one of them is in the zero state. In case the triggers 2 and 3 are in a single state (i.e. there is a high level on the unit arms of the triggers), the signal from the trigger output / (Fig. 2 b) sets the trigger 4 to the single state (Fig. 2 g). The signal from the output 23 on the feedback circuit, acting on the input 24 of the trigger 2, keeps this trigger in the zero state at the moment when the trigger 4 switches to the “zero” state.

The output signal (Fig. 2 d) appears at the output of the AND-NE 10 circuit at the moment of arrival of one of the pulses of the sequence (Fig. 2 a), coincides in time with the state of the decade 1001 and is held at the output until the moment of switching decades to state 0000.

Thus, the circuit functions as a decimal counter.

When the circuit operates as a decade with a phase-impulse presentation of information, the state of the decade is determined by the phase position of the output signal with respect to a certain (reference) sequence (Fig. 2) whose frequency is f ™: Y. In FIG. 2 shows that the circuit is in the state of "nine.

To record information in a decade, it is enough to send a signal to the zero-reset trigger bus 5 to give a signal in the required phase relation with the reference pulse train. FIG. Figure 3 shows that before the recording signal was sent, the nine (FIG. 3 e) decade was in the state of 1, whereby the output pulse coincided in time with the phase constant of one.

At the moment when the recording signal is applied on bus 5, all binary bits are set to zero. After the recording signal is removed, the recalculation is resumed and at the output of the decade a signal appears in phase with the constant "nine" in accordance with the recorded number.

In order to recalculate control of the circuit in the forward direction, it is enough to send a direct counting signal to bus 13 (FIG. 3 g) that does not coincide in time with any of the clocks, while simultaneously authorizing, to send its signal to control bus 12.

This is analogous to adding one to the number stored per decade, since the appearance of such an impulse at the counting input of the decade leads to additional switching

during the time interval between the pulses of the reference sequence and, consequently, to a shift in the phase of the output signal to a larger side (Fig. 3 a-e). The counting pulses must be applied in the interval between the constants "zero and" nine. If an impulse (Fig. 3 and) is fed to the bus // with an enable signal on bus 12, the duration of which is sufficient to overlap two pulses of a clock sequence in time, this is similar to applying a counting pulse, as this reduces the number of switches per unit decade during the time interval between the pulses of the reference sequence and, consequently, the phase shift of the output signal in a smaller direction (Fig. 3 a-e).

Subject invention

A decade counting device implemented on transistor-transistor elements, containing triggers, as well as an input logic block, made on the basis of

"AND - NOT" circuits, characterized in that, in order to extend the functionality, as well as reduce external communications by using phase-impulse information, it contains an output driver built on the basis of the "AND-NOT, one of the inputs of which is connected to the counting input of the decade, and the remaining inputs are connected to single inputs of the first and fourth triggers, the output of this circuit is “AND NOT connected to the output signal bus, and the counting pulse bus through the inverter and the control pulse bus permanently connected to the input circuit "AND-input logic unit, an output

which is connected to one of the inputs of another circuit “NAND, the second input of which is connected to the clock bus, and the output to the counting input of the decade.

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