JPS6038905B2 - Timing signal extraction circuit - Google Patents

Timing signal extraction circuit

Info

Publication number
JPS6038905B2
JPS6038905B2 JP51120772A JP12077276A JPS6038905B2 JP S6038905 B2 JPS6038905 B2 JP S6038905B2 JP 51120772 A JP51120772 A JP 51120772A JP 12077276 A JP12077276 A JP 12077276A JP S6038905 B2 JPS6038905 B2 JP S6038905B2
Authority
JP
Japan
Prior art keywords
timing signal
signal
phase
circuit
extraction circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51120772A
Other languages
Japanese (ja)
Other versions
JPS5345912A (en
Inventor
良充 岡野
薫行 赤木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP51120772A priority Critical patent/JPS6038905B2/en
Publication of JPS5345912A publication Critical patent/JPS5345912A/en
Publication of JPS6038905B2 publication Critical patent/JPS6038905B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 一定角Qoの奇数倍の位相変化をする差動位相変調波(
以下受信キャリアと呼ぶ)の同期検波回路において、一
つの位相情報を形成するータィムスロットの中の符号間
干渉の最も少ない位置でその位相情報を検波することが
検波回路の特性を決める重要な要素である。
[Detailed description of the invention] A differential phase modulation wave (
In the synchronous detection circuit of the received carrier (hereinafter referred to as the received carrier), one phase information is formed - detecting that phase information at the position where intersymbol interference is least in the time slot is an important factor that determines the characteristics of the detection circuit. It is.

このため、タイムスロットの検波位置を決めるタイミン
グ信号は良質のものが必要となってくる。本発明はこの
タイミング信号を抽出するタイミング信号抽出回路に関
するものである。従来、受信キャリアの両側帯波の差信
号を用いてあるし、は復調されたべ−スバンド信号の変
化点を用いてタイミング信号が作成されていた(文献:
データ伝送回路日刊工業新聞社林龍彦他2名著P91〜
P98)。
Therefore, the timing signal that determines the detection position of the time slot needs to be of high quality. The present invention relates to a timing signal extraction circuit that extracts this timing signal. Conventionally, the difference signal between both sideband waves of the received carrier was used, and the timing signal was created using the change point of the demodulated baseband signal (Reference:
Data transmission circuit Nikkan Kogyo Shimbun Tatsuhiko Hayashi et al. 2 authors P91~
P98).

前者の方法で作成されたタイミング信号は以下の欠点が
あって。受信キャリアが搬送回線を経由すると、受信キ
ャリアの両側帯波はそれぞれ群遅延歪の影響を受け、こ
のため両側帯波の差信号はその位相を変えることになり
、差信号より作成したタイミング信号は結果的にタイム
スロットの位相情報を検波する位置を変化させることに
なる。後者の方法で作成されたタイミング信号には以下
の欠点があった。受信キャリアにある特定の位相情報し
かない場合、復調されたベースバンド信号に変化点がな
くなり、その結果タイミング信号を得ることが出来ない
。本発明の目的は前記の問題点を解決したタイミング信
号抽出回路を提供することにある。
The timing signal created by the former method has the following drawbacks. When the receiving carrier passes through the carrier line, both sideband waves of the receiving carrier are affected by group delay distortion, so the difference signal of the both sideband waves changes its phase, and the timing signal created from the difference signal is As a result, the position at which time slot phase information is detected is changed. Timing signals created by the latter method had the following drawbacks. If the received carrier has only certain phase information, there will be no changing points in the demodulated baseband signal, and as a result, a timing signal cannot be obtained. SUMMARY OF THE INVENTION An object of the present invention is to provide a timing signal extraction circuit that solves the above problems.

本発明は1タイムスロットおきの受信キャリアを検波し
、タイミング信号を抽出するタイミング信号抽出回路で
ある。
The present invention is a timing signal extraction circuit that detects a received carrier every other time slot and extracts a timing signal.

一般にQ。=360o/2n位相変化している位相変調
波に対しnてし・倍することにより位相変化点のない信
号となることが知られている。これによりQ。=360
o/2nの奇数倍の位相変化をする位相変調波を(n−
1)てし・倍すれば、隣せつするタイムスロット間の位
相差は180oとなる。この信号を同期検波することに
よりタイミング信号を抽出することが出釆る。第1図は
遅延検波した後同期検波することによりタイミング信号
を抽出する方式である。本実施例の各部の波形を第2図
に示す。
Generally Q. It is known that by multiplying a phase modulated wave having a phase change of =360o/2n by n, a signal without a phase change point can be obtained. This results in Q. =360
A phase modulated wave with a phase change of an odd multiple of o/2n is expressed as (n-
1) Multiplying by 1, the phase difference between adjacent time slots becomes 180o. The timing signal can be extracted by synchronously detecting this signal. FIG. 1 shows a method of extracting a timing signal by performing delayed detection and then synchronous detection. FIG. 2 shows waveforms at various parts in this example.

本実施例は900の奇数倍(1,3・・・倍)の位相変
化(90o,270o)をする2相差動位相変調波(受
信キャリア)からタイミング信号を抽出するタイミング
信号抽出回路である。510の入力端子から受信された
第2図aの如く位相変化している受信キャリア第2図b
は、530のアナログ遅延回路にて第2図cの如く受信
キャリア周波数の(1/4)サイクルだけ遅延する。
This embodiment is a timing signal extraction circuit that extracts a timing signal from a two-phase differential phase modulation wave (received carrier) having a phase change (90o, 270o) of an odd number multiple of 900 (1, 3, . . . times). The receiving carrier received from the input terminal of 510 and having a phase change as shown in Fig. 2a, Fig. 2b
is delayed by (1/4) cycle of the received carrier frequency in an analog delay circuit 530 as shown in FIG. 2c.

540の検波回路はこの信号にて受信キャリアを検波し
第2図dなるサブ受信キャリアを作成する。
A detection circuit 540 detects the received carrier using this signal and creates a sub-received carrier shown in FIG. 2d.

550の排他論理和回路はこの信号とサブ復調用キャリ
ア(復調用キャリアの2倍の周波数)第2図eと排他論
理和をとり、第2図fになる信号を作る。
The exclusive OR circuit 550 performs an exclusive OR with this signal and the sub demodulation carrier (twice the frequency of the demodulation carrier) (e) in FIG. 2 to produce a signal as shown in FIG.

560の基本波抽出回路はこの信号から第2図gなる信
号の基本波を抽出する。
The fundamental wave extraction circuit 560 extracts the fundamental wave of the signal g in FIG. 2 from this signal.

一般に360o/2n(n=3・・・の正数)奇数倍(
1,3,5・・・倍)で3600以下の2n‐1相の位
相変化する受信キャリアからタイミング信号を抽出する
場合は第3図580に示した判別回路を550の排他論
理和回路と560の基本波抽出回路の間に配置す。
Generally, 360o/2n (a positive number where n=3...) odd number times (
When extracting a timing signal from a received carrier whose phase changes in a 2n-1 phase of 3600 or less by a factor of 1, 3, 5, etc., the discrimination circuit shown in FIG. between the fundamental wave extraction circuit.

以上説明した如く、一タイムスロットおきの受信キャリ
アを検波し、この信号を用いてタイミング信号を作成し
たことにより、いかなる位相情報に対してもタイミング
情報が得られ、しかもタイムスロットと1対1の対応を
することから、位相情報を検波する位置を変えない。
As explained above, by detecting the received carrier every other time slot and creating a timing signal using this signal, timing information can be obtained for any phase information, and moreover, it is possible to obtain timing information for any phase information. Therefore, the position where phase information is detected does not change.

即ち検波回路の特性を常に最良の状態に保つことが出来
、良好なデータ伝送を可能にならしめることとなる。
That is, the characteristics of the detection circuit can always be kept in the best condition, making it possible to perform good data transmission.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
第1図の各部の波形図、第3図は判別回路を示すブロッ
ク第4図および第6図は4相位相変調波からタイミング
を抽出するための回路図およびそのタイムチャート、第
5図および第7図は8相位相変調波からタイミングを抽
出するための回路図およびそのタイムチャートである。 図中、510,52川ま入力端子、540は検波回路、
530は遅延回路、550は排他論理和回路、570は
出力端子、56川ま基本波抽出回路、580は判別回路
、581,583・・・は遅延回路、582,584…
は排他論理和回路である。簾′図 第3四 多2四 弟4函 労7 5 図 努J囚 第7函
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG. 3 is a block diagram showing a discrimination circuit. FIGS. 5 and 7 are circuit diagrams and time charts for extracting timing from 8-phase modulated waves. FIGS. In the figure, 510 and 52 are input terminals, 540 is a detection circuit,
530 is a delay circuit, 550 is an exclusive OR circuit, 570 is an output terminal, 56 is a fundamental wave extraction circuit, 580 is a discrimination circuit, 581, 583... are delay circuits, 582, 584...
is an exclusive OR circuit. Blind drawing No. 3, 24 brothers, 4 boxes, 7 5 Zutsutomu J Prisoner No. 7 box

Claims (1)

【特許請求の範囲】[Claims] 1 360°/2^n(n=3,4…)の奇数倍(1,
3,5…倍)の位相変化する2^n^−^1相差動位相
変調波の同期検波回路に用いられるタイミング信号抽出
回路において、前記位相変調波をその周波数の1/4サ
イクル遅延させる手段と、 その遅延した信号にて前記
位相変調波を遅延検波する手段と、 該遅延検波出力を
該位相変調波の2倍の周波数の復調用キヤリアで同期検
波する手段と、 この同期検波出力に遅延を与える手段
と該遅延した信号と前記同期検波出力との積をとる手段
とを有する信号作成回路を(n−2)段縦続接続しかつ
前記各信号作成回路の各遅延手段の遅延がそれぞれ前記
位相変調波の1/8サイクル、1/16サイクル…1/
2^nサイクルになるよう構成された基本パルス作成手
段と、 このパルス作成手段の出力からタイミング信号
を作成する手段とから構成されたことを特徴とするタイ
ミング信号抽出回路。
1 Odd multiple of 360°/2^n (n=3,4...) (1,
In a timing signal extraction circuit used in a synchronous detection circuit for a 2^n^-^1 phase differential phase modulated wave whose phase changes by 3, 5... times), means for delaying the phase modulated wave by 1/4 cycle of its frequency. and means for delay-detecting the phase modulated wave using the delayed signal; means for synchronously detecting the delayed detection output with a demodulation carrier having twice the frequency of the phase modulation wave; (n-2) stages of signal generating circuits having means for giving a product of the delayed signal and the synchronous detection output are connected in cascade, and the delay of each delay means of each signal generating circuit is 1/8 cycle, 1/16 cycle of phase modulated wave...1/
A timing signal extraction circuit comprising a basic pulse generating means configured to have 2^n cycles, and a means for generating a timing signal from the output of the pulse generating means.
JP51120772A 1976-10-07 1976-10-07 Timing signal extraction circuit Expired JPS6038905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51120772A JPS6038905B2 (en) 1976-10-07 1976-10-07 Timing signal extraction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51120772A JPS6038905B2 (en) 1976-10-07 1976-10-07 Timing signal extraction circuit

Publications (2)

Publication Number Publication Date
JPS5345912A JPS5345912A (en) 1978-04-25
JPS6038905B2 true JPS6038905B2 (en) 1985-09-03

Family

ID=14794609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51120772A Expired JPS6038905B2 (en) 1976-10-07 1976-10-07 Timing signal extraction circuit

Country Status (1)

Country Link
JP (1) JPS6038905B2 (en)

Also Published As

Publication number Publication date
JPS5345912A (en) 1978-04-25

Similar Documents

Publication Publication Date Title
JPH0129469B2 (en)
JP3467975B2 (en) Phase detection circuit
CA2110826A1 (en) Clock Recovery Circuit of Demodulator
EP0076008A1 (en) A receiver for FFSK modulated data signals
JPS6189702A (en) Frequency multiplier
JPS61269547A (en) Data signal demodulator
JPS6038905B2 (en) Timing signal extraction circuit
US4213007A (en) Method and apparatus for monitoring a pulse-code modulated data transmission
JPS5974757A (en) Detecting circuit of synchronous signal
US5850161A (en) Digital FM demodulator using pulse generators
JPS5931907B2 (en) Timing signal extraction circuit
JP3154302B2 (en) Phase difference detection circuit
JP3233016B2 (en) MSK demodulation circuit
JPS6319106B2 (en)
JP3344530B2 (en) Digital signal transmission method and digital signal demodulation device
JPH0157539B2 (en)
JPS5975743A (en) Clock regenerating circuit
JPH0129341B2 (en)
JPS58129864A (en) Demodulator for phase modulated signal
JP2765753B2 (en) Digital FSK demodulation circuit
JPS62181556A (en) Digital modulating/demodulating circuit
SU1363501A1 (en) Digital frequency demodulator
JPS60248087A (en) Sampling clock reproducing circuit
JP3037339B2 (en) Clock frequency recovery device for digital data transmission carrier by polyphase PSK modulation
JPS6384347A (en) Generating circuit for phase detecting signal