JPS5931907B2 - Timing signal extraction circuit - Google Patents

Description

[Detailed description of the invention] A differential phase modulation wave (
In a synchronous detection circuit for a received carrier (hereinafter referred to as a received carrier), detecting phase information at a position where intersymbol interference is least in one time slot that forms one phase information is an important factor that determines the characteristics of the detection circuit. It is.

Therefore, the timing signal that determines the detection position of the time slot needs to be of high quality. The present invention relates to a timing signal extraction circuit that extracts this timing signal. Conventionally, a timing signal has been created using the difference signal between both sideband waves of the receiving carrier or the changing point of the demodulated baseband signal (Reference: Data Transmission Circuit, Nikkan Kogyo Shimbun, Tatsuhiko Hayashi et al., 2 authors, 91-98 page).

The timing signal created by the former method has the following drawbacks. When the receiving carrier passes through the carrier line, both sideband waves of the receiving carrier are affected by group delay distortion, so the difference signal of the both sideband waves changes its phase, and the timing signal created from the difference signal is As a result, the position at which time slot phase information is detected is changed. Furthermore, the timing signal created by the latter method has the following drawbacks. If there is only certain phase information in the received carrier, there will be no changing points in the demodulated baseband signal, and as a result, a timing signal cannot be obtained. SUMMARY OF THE INVENTION An object of the present invention is to provide a timing signal extraction circuit that solves the above problems.

The present invention is a timing signal extraction circuit that detects a received carrier every l time slots and extracts a timing signal.

Generally, it is known that by multiplying a phase modulated wave whose phase has changed by α0=3600/2n by 2n, a signal without a phase change point can be obtained.

From this, the phase modulated wave whose phase changes by an odd multiple of α゜ is 2
When multiplied by n-1, the phase difference between adjacent time slots becomes 1800. A timing signal can be extracted by synchronously detecting this signal. The embodiment shown in FIG. 1 is a method in which the timing is extracted by multiplying by (n-l) after detection.

This embodiment is a timing signal extraction circuit that extracts a timing signal from a two-phase differential phase modulated wave (received carrier) whose phase changes by an odd number multiple of 900.

The phase of the reception carrier shown in FIG. 2b supplied from the input terminal 110 of FIG. 1 to the detection circuit 130 is different from that of the demodulation carrier shown in FIG. In a certain time slot as shown in
The time slot changes sequentially to an even number multiple of 02, and an odd number multiple in the next time slot. The second receiving carrier is detected by the detection circuit 130 in Fig. 1.
Figure b is synchronously detected using the demodulation carrier Figure 2 c, and Figure 2 d is
A signal like this is created and supplied to the DC signal creation circuit 140 in FIG. The DC signal generation circuit 140 is composed of a delay circuit 142 and an exclusive OR circuit 143.

The signal in Figure 2 d input from the input terminal 141 is 142
The signal is delayed by (1/4) period of the frequency of the received carrier in a delay circuit to generate a signal as shown in Fig. 2 e.

In the exclusive OR circuit of 143, this signal of Fig. 2 e and the second
The exclusive OR of the signals shown in FIG. 2D is performed, and the signal shown in FIG.

From this signal, a fundamental wave (Fig. 2) (g) of the signal (Fig. 2) (f) is extracted by a fundamental wave extraction circuit 150 (2). The lower part from the center of the signal in FIG. 2g is an even multiple of the phase difference of 90°, and the upper part is an odd multiple. When the received carrier has a phase change that is an odd multiple of 45 parts, the DC signal generation circuit 140 has a configuration in which two circuits each consisting of a delay circuit and an exclusive OR circuit are connected in series, and the first stage delay The delay time of the circuit is (1/4) period (9 minutes) of the receiving carrier frequency, and the subsequent stage is (1/8) period.

Similarly, the receiving carrier is α0=360.

When the phase change is an odd multiple of /2n, the above configuration becomes 21
/4 stages are connected, and the delay time of each delay circuit is 1/4, 1/8, . . . , l/2 frequency period of the receiving carrier.
As explained above, the reception carriers are transmitted every other time slot (in the above description, they are expressed as odd number times and even number times, respectively).

) is used to extract the timing signal. That is, by detecting the received carrier every other time slot and using this signal to create a timing signal,
Timing information can be obtained for any phase information,
Moreover, since there is a one-to-one correspondence with the time slot, the position at which phase information is detected does not change.

That is, the characteristics of the detection circuit can always be kept in the best condition, making it possible to perform good data transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram of each part of FIG. 1. In the figure, 110, 120, 141 are input terminals, 130 is a detection circuit, 140 is a DC signal generation circuit, 142 is a delay circuit,
143 is an exclusive OR circuit, 144 and 160 are output terminals,
150 is a fundamental wave extraction circuit.

Claims (1)

[Claims] 1 In a timing signal extraction circuit used in a synchronous detection circuit for a 2^n^-^1-phase differential phase modulated wave whose phase changes by an odd multiple of 360°/2^n (n = 2, 3, ...), 2^n/ of a signal generating circuit having means for synchronously detecting a phase modulated wave using a carrier for demodulation, means for delaying the detected output, and means for calculating the product of the delayed signal and the detected output; It is constructed by cascading four stages, and the delay of each delay means of each signal generating circuit is 1/4, 1/8...1, respectively.
1. A timing signal extraction circuit comprising: a basic pulse generating means set to /2^n; and a means for generating a timing signal from the output of the pulse generating means.