SU603118A2 - Digital demodulator of signals of relative phase modulation - Google Patents

Description

(54) DIGITAL DEMODULATOR SIGNALS

RELATIVE PHASE MODULATION

The invention relates to radio, in particular, can be used when receiving discrete signals.

According to the main auth. 467463 a digital demodulator of relative phase modulation signals is known, which contains a phase memory unit, its output is connected simultaneously to the first inputs of the phase difference decoder and clock generation unit whose output is connected to one of the matches of the matching circuit, and the outputs of the phase difference decoder through the OR circuit connected simultaneously to the control (direct to the inputs of the phase memory unit and to the control input of the clock shaping node, while the output of the circuit is connected to the second input of the phase difference decoder Opportunity, to the second input of which is connected the information input of the clock shaping node, made in the form of serially connected coincidence block, OR circuit, control pulse selection circuit and clock synchronization block, the second input of the control pulse selection circuit being the control input of the clock shaping node and the information input of the latter is the second input of the match block.

However, the known digital demodulator is not very robust.

In order to improve noise immunity, a signal shaping unit was inserted into the proposed digital demodulator of relative phase modulation signals, connected between another output of the phase memory unit and the corresponding input of the clock shaping node.

FIG. 1 shows the structural electrical circuit of the proposed digital demodulator; in fig. 2 - time diagrams that show the demodulator operation.

Claims (1)

The digital demodulator of the relative phase modulation signals contains a phase memory unit 1, its output is simultaneously connected to the first inputs of the decipheror 2 phase differences and the clock shaping unit 3, the output of which is connected to one of the inputs of the coincidence circuit 4, and the outputs of the decoder 2 phase differences through the OR 5 circuit is simultaneously connected to the control inputs of the phase memory unit 1 and to the control input of the clock generation unit 3, while the output of the phase difference 4 is connected to the second input of the phase difference resolver audio, to the second input of the latter connected to an information input unit 3 generating the clock frequency. The clock generation unit 3 is made in the form of a series of coincident block 6, an OR circuit 7, a control pulse separation circuit 8 and a clock synchronization block 9, the second input of the control pulse extraction circuit 8 being the control input of the clock generation unit 3, the input of this node is the second input of block 4 of coincidence. In addition, in the proposed demodulator, a signal generation unit 10 is inserted, connected between another output of the phase storage unit 1 and the corresponding clock shaping unit 3. The phase memory unit 1 consists of a series-connected master oscillator 11 and frequency dividers 12 and 13 with resetting to the initial state. The digital demodulator of the relative phase modulation signals operates as follows. From a sinusoidal signal (Fig. 2, a), the generated pulses (Fig. 2, b), carrying information about the phase, arrive at a coincidence circuit 4, to the second input of which clock pulses (Fig. 2, 0) are received from the formation unit 3 clock frequency. The coincidence circuit 4 selects one pulse carrying phase information in accordance with the arrival of the clock frequency (Fig. 2, d). This impulse arrives at the decipheror 2 phase difference and is placed at one of its outputs (Fig. 2, e) in accordance with the information received at the second input from the phase memory unit 1 (Fig. 2, e). The same impulse, when it goes through implementation, passes through the scheme OR 5, affects the dividers 12 and 13 of the frequency of the phase memorization unit 1, sets them to their initial state, in-phase with the arrival of the PSM signal in this message (Fig. 2e). For normal operation of the clock shaping unit 3, the signal shaping unit 10 generates a signal that is shifted relative to the main phase difference going to the decider 2 by an angle of .0, while the waiting zone for the appearance of a control pulse (zone I) is somewhat larger than zone of prohibition (zone II, fig. 2, g). The signals at the output of the OR circuit 7 and the control pulse extraction circuit 8 are shown respectively in FIG. 2 3 and. The proposed digital demodulator device allows deciphering the signals of relative phase modulation with a phase change of an angle of L f ± 90 ° with single relative phase modulation and an angle of L H ± 45, It 135 ° with double relative phase modulation, the use of which allows It is possible to reduce the spectrum of spurious emissions, with a large effect to use electromechanical filters with a rectangular characteristic, i.e. reduce phase distortion and improve the noise immunity of receiving information. DETAILED DESCRIPTION OF THE INVENTION Digital demodulator of relative phase modulation signals according to the author's certificate No. 467463, characterized in that, in order to improve noise immunity, a signal conditioning unit is inserted between the other output of the phase memory unit and the corresponding input of the clock generation unit. Sources of information taken into account in the examination: 1. USSR Author's Certificate No. 467463, cl. H 03 K 13/20, 1972. v / VvAAA / WVWVVWVWVWVW lggy11tppl1tppll11PL1Sh11 g1g 1g1pplltg1pplsh1llgga1lppg I I 1 IIIIII