SU855529A2 - Discrete device for phase-shifting - Google Patents

Description

(54) DISCRETE PHASE-MOVING DEVICE

one

The invention relates to a pulse technique and is intended for use in automatic control and monitoring devices in channels of digital tracking systems, in code group generators, in synchronizers of radar and radio navigation indicators.

According to the main author. St. No. 496509, a discrete phase shifter is known comprising a reference oscillator, a counter, S1 and R1 decoders, a switch and a control unit ij.

A disadvantage of this device is its low speed, i.e. the time required to adjust the phase of the output signal by a specified amount. For example, a device in one cycle; recalculating its counter is capable of shifting the phase of the output signal only by One discrete. In this connection, the larger the conversion factor of the counter k, the slower the phase adjustment occurs. In order to shift the phase of the output signal into n samples, it is required to apply n consecutive control pulses and to spend the pure time only on the reorganization of the phase T pTc, where Tz is the counter recalculation cycle. No costs incurred at this time.

on the transmission of control signals. As a result, the range of use of the discrete phase shifter is significantly limited.

The purpose of the invention is to increase rapidly; affinity.

This goal is achieved by the fact that a discrete phase-shifting device containing a reference generator, a counter, a switch, S1 and R1 decoders and a control unit are additionally introduced the first and second interface blocks, 52 and R2 decoders, and S1 and R1 descramblers,

15 are four-input, the output of the counter is connected to the inputs of S2-, R2-decoders and the inputs of the first and second interface blocks, the output of the first of which is connected to the inverse inputs S1, K1-decoders, and the output of the second , R2-decoders, other inputs are connected to the direct and inverse outputs of the torus, and outputs S2 to R2-decoder respectively to the S2 and R-2 inputs of the counter.

By S2 and R2 decoders are meant combinations of AND, OR, NOT logical elements that perform matching functions. For example, you can use two four-input elements I. Under the interface block is meant a digital automaton that performs the function of converting an input signal of arbitrary duration into a signal of a desired duration and transmitting it synchronously with the counter operation on its control input. The essence of the invention in the functional sense is that the device allows, during the counter recalculation cycle, to change the discrete not only by half, but also by the period of the signal of the reference generator from the control signal of an arbitrary length elnosti depending on which of the inputs are supplied with the signal.

The drawing shows a functional diagram of the device.

The device contains a reference generator 1, a counter 2, R1-decoder 3, S) -decoder 4, control unit 5, switch 6, first mating unit 7, S2 decoder 8, second mating unit 9, K2 decoder 10.

The output of the reference generator 1 is connected to the synchronizing C-input of the counter 2 and one of the inputs of the decoders 3 and 4, the outputs of which are respectively connected to the R1 and 51 inputs of the counter 2, the second inputs of the decoder are connected to the output of the counter 2, the control unit 5. The direct output of the switch 6 is connected to one of the inputs of the decoders 4 and 8, and its inverse output is connected to one of the inputs of the decoders 3, 10 and block 5. control, the output of which is connected to the input of the switch 6. The output of the first interface block 7 is connected to the inverse inputs of the decoders 3 and 4, the output of the second interface block 9 is connected to one of the inputs of the decoders 8 and 10, the outputs of which are respectively connected to S2 and K2 -inputs and counter 2. A- and B-device inputs serve to phase shift by + or discrete. B- and G-inputs - for phase shift by + or - 2 discrete.

The device works as follows.

When there are no signals at the control inputs, the switch b is in one of the states, for example, state 0. In this case, the decoder 3. The counter 2 under the influence of the pulses of the reference generator 1 generates pulses with a factor of five. The signals at the inputs A and B of the device provide the phase shift of the output pulses by + or-1 discrete by analogy with the known device. When a signal arrives, for example, at input c, counter 2 one-time changes its conversion factor from 5 to b, at which point the phase of the output signal shifts by + 2D. For a phase shift of the output signal of -2 D, the control signal is fed to the G input.

With the introduction of the aforementioned elements into the device and the input to the inputs C or G of pulses of arbitrary duration, the phase of the output signal can be changed by + or -2, equal to the period

5 signals of the reference generator 1,

The use of the invention allows to increase the speed of the device twice, in connection with which the area of its expansion

0 use. For example, using it in synchronizers-packs of impulses can be reduced by half the minimum periods between adjacent impulses in packs. In addition to this, the possibility of varying the control signals to change the phase of the output signal over a more complex structure with a higher tuning rate is expanded.

Claims (1)

Invention Formula Discrete phase-shifting device according to ed. St. No. 496509, which means that, in order to improve speed, the first and second interface blocks, S2 and R2 decoders, and S1 and K1 decoders are additionally introduced into it. made four-input, the output of the counter is connected to the inputs of S2-, R2-decoders and the inputs of the first and second interface blocks, the output of the first of which is connected to the inverse inputs of S 1-, R1-decoders, and the output of the second one R2 decoders, the other inputs of which are connected respectively to the direct and inverse outputs of the switch, and the outputs of the S2 and R2.-decoders respectively to the 52 and RZ-BHodes of the counter. Sources of information taken into account in the examination 1. USSR author's certificate No. 496509, cl. G 01 R 25/04, 12.02.74.