SU367562A1 - A DEVICE FOR RECEIVING SIGNALS WITH FREQUENCY-PHASE MANIPULATION- '* "^ <*" i' ^. '' *> & G • '^ •• tA:' - "i" * "V • '' i - *. V.'V /! 'WOr ..' EHTH04E; •• cm - Google Patents

Description

I

Apparatuses for receiving discrete signals in frequency-phase telegraphy channels are known, comprising filters, frequency and phase demodulators, a decoding unit, a synchronization system, a regenerator, a frequency and phase jump adder, and a signal splitter.

A disadvantage of the known devices is that they do not provide the required demodulation accuracy.

In order to improve the demodulation accuracy in the proposed device, frequency and phase demodulators are connected in parallel to the output of the oscillation filter, the outputs of which are connected in series to a pulse shaper and a collecting stage with a delay element half the binary mark, and to the output of the second frequency oscillation filter in parallel frequency and phase modulators with pulse formers connected to an adder. In this case, the output of the device adder is connected in series with a delay element and a signal separator.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - phase diagramd diagrams for the device operation.

The device consists of a frequency demodulator L including a band-pass filter 2 frequencies / 1, a band-pass filter 3 frequencies fz, frequency detectors 4 and 5; phase demodulator 6, containing phase detectors 7 and S for oscillations with frequencies / i and / a, respectively, lines 9 and 10 of the delay of signals with frequency / 1 and / 2, respectively, for a time equal to half the duration of the chip TO; block and decoding, including the driver 12 and 13 pulse jumps

detected by the corresponding frequency voltage detector, shapers of 14 and 15 pulses of phase jumps of signals with frequency / 1 and / 2, respectively, lines 16 and 17 of pulse delays by 0.5, logical

the elements OR 18 and 19, the amplifier 20, the adder 21 of the jumps of the frequency and phase jumps, the output of which is connected in series with the delay element 22 0.5 TO (a trigger with one steady state), the regenerator 23

and separator 24 information channels.

The clock synchronization signal generating unit 25 includes a generator 2x of a doubled clock frequency 2Fo, a frequency correction element 27 of a clock signal, device 0

In the 28 comparison of the clock signal and the signal at the output of the regenerator, the driver of 29 pulses with a clock FO and twice the clock 2Fo clock frequencies.

The phased diagrams (see Fig. 2) assume the following notation:

30 characters of the transmitted message;

31- send signal with a frequency fi at the input of the receiving device;

32- send signal with frequency fz at the input of the receiving device;

33- signal on the output of the frequency detector 4;

34 is the signal at the output of the frequency detector 5;

35-sync pulses with a double clock frequency of 2Fo;

36- pulse frequency jumps of the signal 33;

37- pulses 36, delayed by 0.5 TO; 58 - signal at the output of the logical element “OR 18;

39 pulses frequency jumps of the signal 34;

40 signal at the output of the phase detector 7;

41- pulses of phase jumps of the signal 31;

42- pulses 41, delayed by 0.5 o;

43- signal at the output of the logical element “OR 19;

44- signal at the output of the phase detector S;

45 pulses of phase jumps of signal 32;

46 pulses of phase jumps of the received signal;

47- signal at the output of the adder 21;

48 signal at the output of the trigger 22 and the regenerator 23;

49 characters of the received message;

50-sync pulses with a clock frequency FO;

51- characters of channel I messages;

52- characters of channel II messages.

The same designations on the block diagram of the device (see FIG. 1) show the passage of the corresponding signals between the circuit elements.

The received signal with a combined frequency-phase manipulation of two oscillations with an arbitrary and independent carrier frequency spacing after filtering in band-pass filters 2 and 5 is fed simultaneously to frequency detectors 4 and 5 and phase detectors 7; eight.

The detected by the frequency detectors 4 and 5, the voltages 33 and 34 are fed to the inputs of the drivers 12 and 13 pulses of the frequency jumps of the signal, respectively.

The pulse sequence 36 of the jumps of the detected voltage 33 of the signal 31 with the first frequency fi is subjected to logical processing using the logic element OR 18, the first input of which is connected to the driver 12 directly, and the second input through the signal delay line 16 by 36 . After that, the signal 55 from the output of the logic element “OR 18 is fed to the first input of the adder 21.

Pulse sequence of 39 jumps of the detected signal voltage 34

32 with the second frequency fa is fed to the second input of the adder 21.

Impulses 36; 39 correspond to jumps (changes) in the frequencies of signals 31; 32 at the boundaries of the code groups.

In order to detect phase jumps of the received oscillations 31 and 32, these signals are multiplied at phase detectors 7 and 8 with delay lines 9 10 by 0.5, at their second inputs. Phase detectors 7 and 8 detected by voltage 40 and 44, respectively, are fed to the inputs of shapers of 14 and 15 phase jump pulses of signals with frequencies fi and fa. “OR 19, the first input of which is connected to the driver 14, and the second input through the signal delay element 17 of the signal 41 by 0.5 then. After that, the signal 43 from the output of the logic element “OR 19 is fed to the third input of the adder 21.

A sequence of pulses 45 jumps of the detected voltage 44 of signal 32 with a second frequency fz is fed to the fourth input of the adder 21.

Impulses 41; 45 and 46 correspond to phase jumps of signal 31; 32 at the boundaries of the code groups.

After the output of the adder 21, a sequence of 47 pulses is formed, which characterizes the jumps 38; 39 frequencies and 46 phases of the received signal, from which by means of the trigger 22 with one steady state and the regenerator 23 the signal 48 is obtained in the form of a potential form of the transmitted message 30.

A separator 24 of information channels converts a sequence of characters 49 of a received message into two parallel sequences of 51 and 52 characters of messages

I and II channels.

The clock pulses 35 with doubled clock frequency 2Fi) synchronization are supplied from the output of shaper 29 to the second inputs of shaper 12; 13; 14; 15, the regenerator 23 and the separator 24, and the sync pulses 50 with a clock frequency of FU - to the third input of the separator 24.

Subject invention

A device for receiving signals with frequency-phase manipulation, formed by manipulating two independent phase oscillations with an arbitrary frequency spacing, in which a combination of signals of two units with an arbitrary number of zeros is transmitted at the first frequency, the combination of signals from one and zero with an arbitrary number of zeros is transmitted at the second frequency, and when these combinations are repeated, the phase of the emitted oscillations turns over at the boundaries of the combinations of the same name, containing filters, frequency and phase demodulators, b decoding and synchronization locks, regenerator, frequency and phase jump adder, signal splitter, characterized in that, in order to increase the demodulation accuracy, the output frequency and phase demodulators in parallel are connected to the output of the first connected shaper pulses and a collective cascade with a delay element for half a binary mark, and the output frequency filter of the second frequency is connected in parallel with the frequency and phase, modulators with f rmirovatel E pulses coupled to adder prpchem at the output of said adder connected in series delay element and signal splitter.

FIG. 2