JPH0317721A - Signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To quickly obtain a synchronizing signal by sampling the signal which is earlier activated between the signals sampled by a synchronizing clock signal and the signal sampled with the inverted value of the former signal. CONSTITUTION:An AND circuit 5 is changed to a low level from a high level by the signal which is earlier changed to a low level from a high level (activated) between those output signals outputted from the output terminals of the FF 1 and 2. An FF 3 samples the output signal of the circuit 5 at the time of rising a synchronizing clock signal 101. Thus the FF 3 samples the output signal that is earlier changed to a low level from a high level (activated) between those output signals of the FF 1 and 2 at the time of rising the signal 101. As a result, this signal that is earlier changed is outputted by the FF 3 as a synchronizing signal 102.

Description

[Detailed description of the invention] The present invention relates to a signal synchronization circuit that synchronizes signals in a computer.

BACKGROUND ART Conventionally, as shown in FIG. 3, this type of signal synchronization circuit consists of two stages of flip-flops 7 and 8, in which the input signal 100 to be synchronized is input to the synchronization clock signal in the previous stage flip-flop 7. The synchronizing signal 103 is obtained by sampling the output signal of the flip-flop 7 using the synchronizing clock signal 101 in the subsequent flip-flop 8.

In such a conventional signal synchronization circuit, one of the rising and falling points of the synchronizing clock signal 101 is used, and two stages of flips 7 and lobes 7 and 8 are used in series. , there is a drawback that the synchronization signal 103 can only be obtained with a clock width of one period or more.

Furthermore, if the input signal l00 to be synchronized and the synchronization clock signal 101 change simultaneously, the output of the flip-flop 7 at the previous stage becomes unstable, and the correct synchronization signal 100 changes.
There is a drawback that 3 is obtained only after 2 synchronous clock widths.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the problems of the conventional circuits as described above, and an object of the present invention is to provide a signal synchronization circuit that can obtain a correct synchronization signal faster than the conventional circuit.

Structure of the Invention The signal synchronization circuit according to the present invention includes a first flip-flop that samples an input signal to be synchronized using a synchronization clock signal, and a first flip-flop that samples the human input signal using an inverted value of the synchronization clock signal. and a third flip-flop that samples the signal that becomes active first among the output signals from the first and second flip-flops using the synchronization clock signal. shall be.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are block diagrams showing the configuration of an embodiment of the present invention. FIG. 1 shows the configuration of a signal synchronization circuit for active low signals, and FIG. 2 shows the configuration of the signal synchronization circuit for active high signals.

In Fig. 1, the blip prop 1 has an inverter 4.
In synchronization with the synchronizing clock signal 101 inputted from the human clock terminal C, the input data terminal D
An input signal l00 to be synchronized inputted from is taken in. That is, the flip-flop 1 samples the input signal 100 to be synchronized at the falling edge of the synchronization clock signal 101.

The flip-flop 2 also receives an input signal lO to be synchronized which is input from the input data terminal D in synchronization with the synchronization clock signal 101 which is manually input from the input clock terminal C.
O is taken in. That is, the flip-flop 2 samples the human input signal 100 to be synchronized at the rising edge of the synchronization clock signal 101.

The AND circuit 5 changes from high to low depending on the output signal outputted from the output terminals Q of the flip-flops 1 and 2, which changes from high to low (becomes active) first.

The flip-flop 3 receives an output signal from the AND circuit 5 input from the input data terminal D in synchronization with a synchronizing clock signal lot input from the input clock terminal C.

That is, since the flip-flop 3 samples the output signal from the AND circuit 5 at the rising edge of the synchronization clock signal 101, the flip-flop 3 samples the output signal from the flip-flops 1 and 2 from high to low first. The output signal that has changed (became active) is sampled at the rising edge of the synchronization clock signal lot.

Therefore, in the flip-flop 3, the signal that changes quickly (the signal that becomes active first) is used as the synchronization clock signal Lo.
Since the signal is sampled at the rising edge of t, this rapidly changing signal is output as the synchronization signal 102.

FIG. 4 is a time chart showing the operation of the signal synchronization circuit of FIG. 1. As shown in FIG. 4, in the signal synchronization circuit according to the embodiment of the present invention, when the input signal 100 changes from high to low in the high section of the synchronization clock signal lot, the conventional circuit shown in FIG. The synchronization signal 102 can be obtained earlier than in the case of (see the time chart in FIG. 5).

However, if the input signal 100 changes from low to high during the high period of the synchronization clock signal 101, the fifth
This is similar to the case of the conventional circuit shown in the figure.

In FIG. 2, the flip-flop 1 has an inverter 4.
In synchronization with the synchronization clock signal lot input from the input clock terminal C, the input data terminal D
An input signal 100 to be synchronized that is input from is captured. That is, the flip-flop 1 samples the input signal l00 to be synchronized at the falling edge of the synchronization clock signal 101.

The flip-flop 2 also receives an input signal 10 to be synchronized which is input from an input data terminal D in synchronization with a synchronization clock signal 101 which is input from an input clock terminal C.
0 is captured. That is, the flip-flop 2 samples the human input signal 100 to be synchronized at the rising edge of the synchronization clock signal 101.

The OR circuit 6 changes from low to high depending on the output signal that first changes from low to high (becomes active) among the output signals output from the output terminals Q of the flip-flops 1 and 2, respectively.

The flip-flop 3 receives an output signal from the OR circuit 6 input from the input data terminal D in synchronization with the synchronizing clock signal 101 input from the input clock terminal C.

That is, since the flip-flop 3 samples the output signal from the OR circuit 6 at the rising edge of the synchronization clock signal 101, the flip-flop 3 samples the output signal from the flip-flops 1 and 2 from low to low first. The output signal that has changed to high (becomes active) is sampled at the rising edge of the clock signal lOl.

Therefore, in the flip-flop 3, the signal that changes quickly (the signal that became active first) is used as the synchronization clock signal 10.
Since the signal is sampled at the rising edge of 1, this rapidly changing signal is output as the synchronization signal 102.

FIG. 6 is a time chart showing the operation of the signal synchronization circuit of FIG. 2. As shown in FIG. 6, in the signal synchronization circuit according to the embodiment of the present invention, when the input signal 100 changes from low to high during the high section of the synchronization clock signal 101, the conventional circuit shown in FIG. The synchronization signal 102 can be obtained earlier than in the case of (see the time chart in FIG. 7).

However, when the input signal t00 changes from high to low during the high period of the synchronization clock signal L, the situation is similar to that of the conventional circuit shown in FIG.

In addition, in the signal synchronization circuit for the active low signal and the signal synchronization circuit for the active high signal according to an embodiment of the present invention, when the human input signal 100 changes in the low section of the synchronization clock signal 101, the conventional signal synchronization circuit is used. The same is true for circuits.

In this way, the output signal from the flip-flop 1 using the rising edge of the synchronizing clock signal lOl and the output signal from the flip-flop 2 using the falling edge of the synchronizing clock signal lot
By sampling the signal that changed first (the signal that became active first) in the flip-flop 3 at the rising edge of the synchronization clock signal 101, the correct synchronization signal 102 can be obtained more easily than before. You can get it quickly.

Effects of the Invention As explained above, according to the present invention, an input signal to be synchronized can be a signal sampled by a synchronization clock signal, and a human input signal can be a signal sampled by an inverted value of the synchronization clock signal. By sampling the signal that becomes active first using the synchronization clock signal, there is an effect that a correct synchronization signal can be obtained more quickly than before.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the structure of an embodiment of the present invention, FIG. 3 is a block diagram showing the structure of a conventional example, and FIG. 4 is a block diagram showing the operation of the signal synchronization circuit of FIG. 1. 5 and 7 are time charts showing the operation of the conventional example, and FIG. 6 is a time chart showing the operation of the signal synchronization circuit of FIG. 2. Explanation of symbols of main parts 1 to 3... Flip-flop 4... Inverter 5... AND circuit 6... OR circuit

Claims (1)

[Claims] (1) a first flip-flop that samples an input signal to be synchronized using a synchronization clock signal;
a second flip-flop that samples the input signal using an inverted value of the synchronization clock signal;
and a third flip-flop that samples the signal that becomes active first among the output signals from the second flip-flop using the synchronization clock signal.