JPH05235710A - Gate device - Google Patents

Abstract

PURPOSE:To generate an output pulse as soon as a gate signal is active independently of a timing relation between a clock signal and a gate signal. CONSTITUTION:A flip-flop 18 blocks a gate signal B based on a clock signal A. A gate circuit 12 passes through the clock signal A in response to an output signal C of the flip-flop 18. A frequency divider 20 frequency-divides the output signal D of the gate circuit 12 and an exclusive OR gate circuit 22 receives an output signal E of the frequency divider 20 and the output signal C of the flip-flop 18 and generates an output signal F.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate device which allows a clock signal to pass only when the gate signal is active.

[0002]

Gating devices that pass a clock signal only when the gate signal is active are used in various electronic devices. For example, an arbitrary waveform generator stores digital data corresponding to an arbitrary analog waveform in a memory, reads digital data from the memory according to the count value of an address counter, and converts the digital data into an analog waveform. This arbitrary waveform generator has a function of sequentially outputting analog waveforms (arbitrary waveforms) only while the gate signal is active (for example, high level period). To achieve this function, the gating device needs to provide the clock signal to the address counter only while the gating signal is active.

A conventional example of a gate device used in this way is shown in FIG. The clock generator 10 generates a clock signal B having an appropriately set frequency. The AND gate 12 passes the clock signal B from the clock generator 10 and generates the output signal C at the output terminal 16 only when the gate signal A supplied to the terminal 14 is active (in this case, high level). To do. The timing relationship between these signals A, B and C is shown in FIG.

[0004]

In the gate device as shown in FIG. 3, the gate signal A and the clock signal B are irrelevant in time and may not be synchronized with each other. In such a case, the maximum period from the time point T1 when the gate signal A becomes active to the time point T2 when the output signal C is generated is one half of the cycle of the clock signal B. Therefore, when the gate device is used in the above arbitrary waveform generator,
Even if the gate signal becomes active, the arbitrary waveform will not be generated immediately.

Therefore, an object of the present invention is to provide a gate device which can generate an output pulse as soon as possible when the gate signal becomes active regardless of the timing relationship between the clock signal and the gate signal.

[0006]

According to the gate device of the present invention, the flip-flop 18 clocks the gate signal with the clock signal, that is, latches the gate signal with the edge of the clock signal. The gate circuit 12 passes the clock signal according to the output signal of the flip-flop 18. The clock signal that has passed through the gate circuit 12 is divided by the frequency divider 20. Exclusive OR (ex
The exclusive OR) gate circuit 22 receives the output signal of the frequency divider 20 and the output signal of the flip-flop 18, performs exclusive OR processing, and generates an output signal.

[0007]

According to the present invention, the exclusive OR gate circuit 22
Therefore, when the output signal of the flip-flop 18 becomes active, the gate device can immediately generate the output signal. Further, since the frequency divider 20 is used, the frequency of the clock signal is higher than the frequency originally required, and the frequency divider 20 is provided between the gate circuit 12 and the exclusive OR gate circuit 22. ing. Therefore, the period from the activation of the gate signal to the generation of the first output pulse is 2
Since it is less than or equal to one-half cycle, it is a significant improvement over the above-mentioned prior art.

[0008]

1 is a block diagram of a preferred embodiment of the present invention, and FIG. 2 is a timing diagram illustrating the operation of FIG. The clock generator 10 generates a clock signal A having a frequency N times higher (N is an integer of 2 or more) higher than the originally required frequency. In this example, N = 2. The flip-flop 18 latches the gate signal B supplied from the gate terminal 14 to the data terminal D at the falling edge of the clock signal A supplied to the inverted clock input terminal C, and outputs the latch output signal C to the Q terminal. Occurs in. Therefore, even if the gate signal B activated at the time T1 is not synchronized with the clock signal A, the output signal C remains at the time T.
It becomes active at 2 and synchronizes with the clock signal A.

The gate circuit 12 is a flip-flop 1
When the output signal C of 8 is active (high level in this case), the clock signal A is passed to generate the output signal D. Since the signals A and C are synchronized, the gate circuit 1
The output signal D of 2 is complete in its period from the first output pulse (note that the low level of the signal D between times T2 and T3 is not timed). The frequency divider 20 is an N-ary counter that divides the output signal D of the gate circuit 12 into 1 / N, and uses the carry signal as the output signal E. The exclusive OR gate circuit 22 receives the signals C and E, performs exclusive OR processing, and generates an output signal F at the output terminal 16. The time T4 at which the output signal E of the frequency divider 20 is generated lags behind the time T2 at which the output signal C of the flip-flop 18 is generated due to the frequency dividing operation, but due to the operation of the exclusive OR gate circuit 22, Its output signal F occurs at the same time T2 as the output signal C of the flip-flop 18 (ignoring the propagation delay time of each element).

[0010]

As described above, according to the present invention, by the action of the exclusive OR gate circuit, when the output signal of the flip-flop becomes active, the gate device can immediately generate the output signal. Furthermore, the period from the activation of the gate signal to the generation of the first output pulse is 2 times that of the clock signal having a frequency higher than the desired frequency.
It can be less than one-half cycle. Therefore, the gate device of the present invention is suitable for use in the arbitrary waveform generator described above.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of a gate device of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG.

FIG. 3 is a block diagram of a conventional gate device.

FIG. 4 is a timing diagram illustrating the operation of FIG.

[Explanation of symbols]

 10 clock generator 12 gate circuit 18 flip-flop 20 frequency divider 22 exclusive OR gate circuit

Claims (1)

[Claims] 1. A flip-flop for clocking a gate signal with a clock signal, a gate circuit for passing the clock signal according to an output signal of the flip-flop, and a frequency divider for dividing the output signal of the gate circuit. Device and an exclusive OR gate circuit for receiving the output signal of the frequency divider and the output signal of the flip-flop.