JPS59123911A - Phase adjusting system - Google Patents

Abstract

PURPOSE:To speed up data transfer between systems by prohibiting operating function of one of two dividing circuits obtained by dividing an external clock, delaying basic operation clock of corresponding another circuit, and conforming the phase of two basic operation clocks. CONSTITUTION:Clock pulse CLK from an external clock source 1 is divided to 1/2 by dividing circuits 2 and 3, and sent to MPU4 and 5 respectively. CLK1 and CLK2 of the output are sent to peripheral units 6 and 7 and a logic gate 8. A timing error signal outputted from the gate 8 is applied to a terminal A of the circuit 3. When the timing error signal is ''0'', i.e. when there is phase difference between signals CLK1 and CLK2, output of the circuit 3 is made ''0''. Accordingly, 1/2 divided clock supplied to MPU2 is stopped for the while and rise-up of the signal CLK2 is delayed and phase adjustment is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a system in which an external clock is used as a dividing signal in two separate systems.

This phase adjustment method for automatically adjusting the phase of the operating clock signal (2 related methods).

[Technology background]

Conventionally, systems with two independent data processing devices (in two systems, internal clock signals that control the basic operations of each data processing device are processed separately from a common external clock signal). Even if the devices are powered on at the same time, for example, there may be a difference in the time it takes to actually generate two internal clock signals, or a difference in the initial state of the frequency divider circuit. It is normal for there to be a phase difference between the internal clock signals (two is one phase).

However, when data or control signals are transferred between two such data processing devices (2).

The clock phase shift between both data processing devices becomes a problem, resulting in the inconvenience of extra transfer time.

[Object and structure of the invention]

An object of the present invention is to detect the phase difference between two basic operating clocks generated by dividing one external clock separately by two devices, and to automatically eliminate the phase difference. Providing an adjustment method (= Yes, the configuration for this is two independent devices each operating with a basic operating clock of the same period and having means for generating the basic operating clock controlled by an external signal. system (with two but a single external clock source).

The output of the external clock source (two frequency dividing circuits connected in parallel with the same frequency division ratio is provided, and the output of the two frequency dividing circuits is used to generate the basic operation of the two independent devices). In addition as a control signal.

2. Providing means for detecting the phase difference between the basic operating clocks of the two independent devices, and inhibiting the operating function of one of the two frequency dividing circuits by the output of the phase difference detecting means (from 2). , one of the corresponding basic operating clocks is delayed, and the phases of the two basic operating clocks are matched.

[Embodiments of the invention]

FIG. 1 shows a circuit according to an embodiment of the present invention, and is shown in FIG. 9.

1 is an external clock source that generates an 8 MHz clock pulse CLK, 2.3 is a 1/2 divider circuit, and 4 is a microprocessor MPUI that has a 1/4 circuit and generates an IMHz pass clock CLK1. , 5) is also 1/4
The microprocessor MPU2゜6, which includes a frequency dividing circuit and generates an IMHz pass clock CLK2, is a system SYSTEMI controlled by a bus clock CLKI, and 7 is another system 8YS'I controlled by a bus clock CL2.
``FltM2, 8 are logic gates.'' to ``2'' indicate signals at the circuit troughs.

8Y8'l'BM1 and SYS'l''EM2 are peripheral devices or other controlled devices, between which the respective bus clocks CLKI, CLK2+= are synchronized.

Data is sent and received. Therefore, CLKI and CL
If synchronization with K2 is not achieved, a time delay may occur in the timing for data transmission and reception.

However, if the 1/4 frequency divider circuit in the MPUI and MPU2 is reset after the power is turned on and then started up, there is variation in the time until it is reset, and the 1/4 frequency divider circuit in the MPUI and MPU2 is reset after the power is turned on. In this case, the initial state of the divide-by-1 circuit becomes irregular. Therefore, between CLKI and CLK2 (=, (I) to (1) as shown in FIG.
The four cases of v) occur.

Logic gate 8 detects the phase difference of %II level between CLKI and CLK2 and feeds back the l/2 frequency divider 3-=timing error signal to control its function.

1/2 frequency divider circuits 2 and 3 are both edge trigger type 7
It may be a flip-flop; for example, in the case of a JK flip-flop, terminal A is input to J.

Terminal B becomes CK large input. This circuit is connected to terminal A42'1
When # is applied, a toggle operation is performed in response to the clock input to terminal B, producing a 1/2 frequency divided output. However, when terminal A is 0 (2), it is 10'
produces an output.

+ CLK2. Therefore, CLKI-'
1', the timing error signal = 10' only when CLK2 = '0', and in all other cases (2 - signal = 111 due to timing).

The timing error signal output from the logic gate 8 is
When the terminal 42 of the l/2 frequency divider circuit 3 is applied and the timing error signal is ゝO', that is.

Between C'LKI and CLK2 (when there is a two-phase difference).

The output of the 1/2 frequency divider circuit 3 is assumed to be 'O''. Therefore.

During this period, the 1/2 branch clock supplied to MPU2-2 is stopped, the rise of CLK2 is delayed, and one phase adjustment is performed.

FIG. 3 is a timing diagram for explaining the operation of the embodiment circuit of FIG. 1. The figure shows the phase relationship (1
), (1), and (IV) are shown separately. The waveform is shown by the dotted line.

This is before phase adjustment, and the solid line waveform shows the result of phase adjustment. For example, 9 phase relationship (It)
In this case, CLK2 has a phase delay of timing (ts-ts). As a result, a timing error signal (■) is generated, and the pulses P, , P, in the 1/2 frequency division ratio (P) are inhibited, and the rising edge of CLK2 (■) is inhibited.

It is delayed until timing t. But this result.

Since complete phase adjustment has not yet been achieved, there is a further phase delay shown in the phase relationship (seal), and the timing t.

It will be adjusted to the correct synchronization position as shown in .

In this way, any phase relationship between CLKI and CLK2 is automatically adjusted (-
It can be controlled in a synchronous state.

Note that the division ratio of the valley branch circuit in the embodiment circuit shown in FIG. (Even if there are two, d2 can be similarly applied.Also, instead of directly controlling the operating function of the 1/2 frequency divider 3 by the timing error signal, a gate is provided before or after the 1/2 frequency divider, You may want to control this.

Furthermore, the present invention can be applied as is to synchronize the clocks of any plurality of systems.

〔Effect of the invention〕

As described above, (25) according to the present invention, the multiplier phase of two independently frequency-divided systems can be quickly and easily calculated (
Synchronization can be achieved from two systems, speeding up data transfer between systems, and simplifying the transfer means.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a clock phase shift, and FIG. 3 is an operation timing diagram of the embodiment of FIG. 1. In the figure, 1 is an external clock source, 2.3 is a 1/2 frequency divider circuit,
4.5 are MPUs each having a 1/4 frequency dividing circuit], MP
U2.6 is SYS'l'EM1, 7 is SY8TFfM2
8 represents a logic gate. Patent applicant Fujitsu Ltd. Representative patent attorney Fumihiro Hase (1 other person) Sai Zzu

Claims (1)

[Scope of Claims] In a system comprising two independent devices each operating with a basic operating clock of the same period and having means for generating said basic operating clock under the control of an external signal (two an external clock source, and the output of the external clock source (two frequency divider circuits with the same frequency division ratio connected in parallel). The outputs of the two frequency divider circuits are respectively connected to the two independent devices In addition to the control number i of the basic operation clock generation means, further C = the basic operation clocks of the two independent devices (means for detecting the phase difference between the two is provided. The output of the phase difference detection means is used to generate the above two clocks). A phase adjustment method characterized by inhibiting the operating function of one of the circuits (secondarily, delaying the corresponding one of the basic operating clocks and aligning the phases of the two basic operating clocks.