JPS61251930A - Processing circuit of digital data - Google Patents

Abstract

PURPOSE:To use effectively the transmission capacity to raise the transmission speed by controlling the transmission with a shift control signal of a prescribed sequence when a data sequence consisting of words whose number of bits exceeds the limited number of bits of a transmission line is transmitted to this transmission line. CONSTITUTION:For example, 10-bit input data is supplied from a terminal 1 to cascaded latches 11, 12, and 13, and a clock CK1 synchronized with input data is supplied from a terminal 4 to latches 11, 12, and 13. Contents L1, L2, and L3 of latches 11-13 are supplied to a phase shifter 2. This shifter 2 generates output data obtained by shifting input data by the number of bits corresponding to a shift control signal phi. 16-bit output data, in this case, generated in the output of the shifter 2 is supplied to a latch 14, and a clock CK2 is supplied to the latch 14 from a control circuit 5. The latch 14 latches the output of the shifter 2 synchronously with the clock CK2, and contents L4 of the latch 14 are sent from an output terminal 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data processing circuit applied to the transmission and recording of digital data.

〔overview〕

The present invention is to control a phase shifter using a shift control signal φ of a predetermined sequence when passing a data sequence consisting of words having a greater (or less) number of bits through a transmission path having a limited number of bits. This eliminates gaps in the backed output data and makes use of the transmission capacity to increase the transmission speed.

[Conventional technology]

For example, when digital data having 12 bits as one word is transmitted via a transmission line with 8 bits, backing as shown in FIG. 7A is used. In FIG. 7, numbers indicate word numbers. As can be understood from Figure 7A, when a word is 12 bits, it is sufficient to always divide this one word into 8 bits and 4 bits, and with relatively simple backing processing, the transmission capacity is wasted. It can be used without any problems.

On the other hand, when digital data of which one word is 10 bits is similarly transmitted via a transmission line with 8 bits, the backing process becomes complicated, so one word is always transmitted as shown in Figure 7B. The data is divided into 8 bits and 2 bits, and one word of data is inserted into a two word section of the transmission line.

[Problem that the invention seeks to solve]

As is clear from FIG. 7B, the conventional processing does not make full use of the transmission capacity of the transmission path (there is a problem that the data transmission speed is low. It has the drawback of not being able to respond when the number changes, and lacks versatility.

Therefore, an object of the present invention is to provide a digital data processing circuit that can fully utilize the transmission capacity of a transmission line and enable high-speed data transmission.

When this invention is applied to the case where data reproduced from a recording medium is transferred to a computer, there is an advantage that preprocessing of unbacking the data using a program on the computer is not necessary.

[Means for solving problems]

The invention provides at least two latches 11.12.13 corresponding to the number of bits of input data and connected in series with each other.
and a shift means 2 to which the outputs from the launches 11, 12, and 13 are supplied in parallel, and generates data φ that sets the shift amount of the shift means 2 based on the number of bits of input data and the number of bits of output data. This is a digital data processing circuit characterized in that the circuit 5 is configured to output output data having a number of bits different from the number of bits of input data.

[Effect]

The shift amount of the shift means 2 is controlled by the data φ, and the output data of the shift means 2 becomes the input data backed up. This control data is based on the number of bits of the input data and the output data. Based on the number of bits of
configurable and can realize a versatile configuration.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In one embodiment of the present invention, the present invention is applied when the data is n (=10 bits) and the number of bits in one word of the transmission path is m (=16 bits).

In Figure 1, 1 is 10 bit parallel (1 word)
Indicates an input terminal to which input data is supplied. This input data is, for example, data reproduced from a digital data recorder. Input data is latched 11, 12, 13
supplied to a cascade of A clock CKI synchronized with input data is supplied from terminal 4 to latches 11, 12, and 13.

Lunch 11, 12, 13. The respective contents Ll, L2, L
3 is supplied to the phase shifter 2.

The phase shifter 2 is composed of a large number of selectors, and generates output data by bit-shifting input data by a number of bits according to a shift control signal φ. 5 is a control circuit that generates a shift control signal φ and a clock CK2. A data bus 7 of the CPU 6 and an address bus 8 of the CPU 6 are coupled to the control circuit 5. A keyboard 10 is provided in association with the CPU 6. In the control circuit 5,
A block signal BLK indicating division of input data into a predetermined number of words is supplied from a terminal 9.

The 16-bit output data generated at the output of phase shifter 2 is supplied to latch 14. The latch 14 is supplied with the clock CK2 from the control circuit 5, and the latch 14 is
The output data of the phase shifter 2 is latched in synchronization with the clock CK2. The content L4 of this latch 14 is taken out to the output terminal 3 as an output. This output data is supplied to the computer via a data bus, for example. An unbacking circuit, which will be described later, is provided on the computer side.

FIG. 2 shows an example of the control circuit 5. As shown in FIG. The control circuit 5 mainly includes a register 21, a RAM 22, and a counter 23. The initial value of the counter 23 is supplied to the register 21 from the CPU 6 via the data bus 7.
This initial value is set in the register 21. A sequence of a shift control signal φ and a mask signal is written into the RAM 22 from the CPU 6 via the data bus 7. This R
When the sequence of the shift control signal φ and the mask signal is first stored in the AM 22, an address signal from the CPU 6 is supplied to the RAM 22 via the address bus 8.

Information on the number of input bits and the number of output bits is given to the CPU 6 by the keyboard 10. Based on this input information, the CPU 6 calculates, based on a general-purpose algorithm,
A sequence of shift control signal φ and mask signal is generated.

When the above settings are made, the counter 2 is stored in the RAM 22.
Addresses from 3 are supplied. A block signal BLK synchronized with input data is supplied to one input terminal of an AND gate 25 via an inverter 24. The ripple carry of the counter 23 is supplied to the other input terminal of the AND gate 25. With the output of this AND gate 25,
The initial value stored in the register 21 is loaded into the counter 23 for each block.

The counter 23 performs a counting operation using the clock CK1, and its output is used as an address signal for the RAM 22.

A shift control signal φ read from the RAM 22 is supplied to the phase shifter 2.

The mask signal read from RAM 22 is provided to flip-flop 26 as a data input.

The mask signal is a signal that has a low level when masking, and a high level when not masking. This flip-flop 26 is supplied with a clock CKI. The output of flip-flop 26 and clock CKI are supplied to AND gate 27.

A clock CK2 is generated at the output of the AND gate 27, and the clock CK2 is supplied to the latch 14.

The operation of one embodiment of the present invention will be explained with reference to FIG. FIG. 3A shows the clock CKI.

When the word numbers of the input data are assigned sequentially starting from 1, the contents L1 of latch 11 and latch 1 are synchronized with clock CKI.
The contents L2 of latch 13 and the contents L3 of latch 13 change as shown in FIG. 3B.

The shift control signal φ read from the RAM 22 of the control circuit 5 when backing 10 bits to 16 bits is:
The result is shown in FIG. 3C. The number of the shift control signal φ indicates the number of bits from the top of the input data of the phase shifter 2 to be shifted. For example, when the shift control signal φ is 0, no shift operation is performed and the upper 16 bits of the input 30 bits (FIG. 3B) are output. Therefore, the 16 bits of the output of phase shifter 2 at this time are:
As shown in the third diagram, the first word consists of 10 bits and the second word consists of 6 bits.

Next, when the shift control signal φ is 6, the input 30 bits (FIG. 3B) are shifted by 6 bits, and 16 bits from the seventh bit from the top of the input data are output.

Therefore, the 1j bits output from the phase shifter 2 at this time consist of 4 bits of the second word, 10 bits of the third word, and 2 bits of the fourth word, as shown in the third diagram. Thereafter, similar operations are performed, and the 16-bit output data of the phase shifter 2 becomes as shown in the third diagram.

Shift control signal φ is read out in synchronization with clock CKI. In FIG. 3C, when the same shift control signals φ are read out successively, the contents of the shift control signals φ are collectively shown.

In this embodiment, the shift control signal φ is (0,
6, 6, 2, 8, 8, 4, 4) sequence.

FIG. 3E shows the clock CK2 from the control circuit 5.

In FIG. 3, the dashed line indicates the masked clock. Output data of phase shifter 2 (Fig. 3D
) is taken into the latch 14 by the clock CK2, so the contents L4 of the latch 14 become as shown in FIG. 3F. As can be seen from FIG. 3F, 10-bit parallel input data is backed up with 16-bit parallel output data without any gaps.

Even if the output data is not shown, it can be stored in a buffer memory such as FIF.
It is also possible to convert the data into data with a constant word clock by supplying it to ○.

The configuration of another embodiment of the present invention will be described below, in which data backed by 16 bits is banked into 10 bits according to one embodiment of the present invention.

In FIG. 4, numeral 31 is an input terminal to which 16-bit banked input data is supplied.

A cascade of latches 41, 42 is connected to the input terminal 31. 32 bits consisting of the contents Lll of latch 41 and the contents L12 of latch 42 are input to phase shifter 32. The phase shifter 32 is supplied with a shift control signal φ read from the RAM 45. The 10-bit output data of phase shifter 32 is supplied to latch 43. The content L13 of the latch 43 is taken out to the output terminal 33.

A clock CKI from the terminal 34 is supplied to the latch 41 . Clock CKI is supplied to clock generation circuit 35. Data and addresses are supplied to the clock generation circuit 35 via a data bus 37 and an address bus 38 of the CPU 36. Further, the block signal BLK from the terminal 39 and the system clock CKIO from the clock oscillator 44 are supplied to the clock generation circuit 35 . The system clock CKIO is also supplied to the CPU 36. Clock CKI2 supplied to latch 42 and clock CK13 supplied to latch 43 and counter 46
is formed by the clock generation circuit 35.

A keyboard 40 provided in association with the CPU 36 inputs the number of bits of input data and the number of bits of output data to be unbacked.

The CPU 36 supplies a sequence of shift control signals φ to the RAM 45 via the data bus 37 based on information input from the keyboard. At this time, a write address is supplied from the CPU 36 to the RAM 2S via the address bus 38, and the sequence of shift control signals φ is stored in the RAM 45.

A sequence of shift control signals φ is read out from the RAM 45 in synchronization with the clock CK13.

FIG. 5 shows the configuration of an example of the clock generation circuit 35. As shown in FIG.

In FIG. 5, 52 indicates a RAM that stores a sequence of mask signals. 53 is a counter that generates the address of the RAM 52.

A sequence of mask signals is stored in the RAM 52 via the data bus 37 of the CPU 36. At this time, the CPU
A write address is supplied from the CPU 36 to the RAM 52 via 36 address buses 38.

When the sequence of mask signals is written to the RAM 52, the CP signal is sent to the counter 53 via the data bus 37.
Initial values are loaded from U36.

This loading is performed by the block signal BLK passed through the inverter 54 and the output signal of the AND gate 55 to which the ripple carry of the counter 53 is supplied. Therefore, the counter 53 is loaded for each block.

The counter 53 counts the clock CKII, and the counter 53 counts the clock CKII.
2 address signals are generated.

In FIG. 5, 59 indicates a shift register. A high frequency system clock CKIO is supplied to the shift register 59 as a shift clock. The input terminal of the shift register 59 is supplied with the output of the SR luff 56 . Clock CK11 is connected to S via inverter 57.
It is supplied to the set input terminal of the R clutch 6. The output F of the shift register 59 is supplied to the input terminal of the SR launch 56 via the inverter 58.

Among the output terminals A to F of the shift register 59, output pulses having different phases taken out from the output terminals C to F are supplied to NAND gates 61, 63, and 62°64.

The outputs of NAND gates 61 and 62 are NAND gate 6
5. Clock CK from NAND gate 65
12 occurs.

The outputs of NAND gates 63 and 64 are NAND gate 6
6. Clock CK from NAND gate 66
13 occurs.

A 4-bit mask signal is sequentially generated from the RAM 52.

Each bit of the mask signal is a signal that becomes low level during masking. Each bit of this mask signal is supplied as a mask signal to each of NAND gates 61.62 and 63.64. Latch 42 at the rising edge of clock CK12
takes in the output of latch 41. The latch 43 takes in the output of the phase shifter 32 at the rising edge of the clock CK13.

The unbacking operation performed by the other embodiment of the present invention shown in FIGS. 4 and 5 above will be explained with reference to FIG. 6.

6A shows the clock CK11, FIG. 6B shows the clock CK12, and FIG. 6C shows the clock CK13.
shows. Among the clocks CK12 and CK13, those indicated by broken lines represent the clocks masked by the mask signal from the RAM 52.

The shift register 59 of the clock generation circuit 35 outputs an output A that sequentially becomes high level within one cycle of the clock CKII.
- Generates F. When the output F is generated, the SR latch 56 is reset by the output F, and the next clock CK
The output of the SR latch 56 remains at a low level until II is supplied. Outputs C, D, E, and F of the shift register 59, whose phases are shifted by one cycle from the system clock CKIO, are used to form clocks CK12 and CK13.

The outputs C and E of the shift register 59 are the clock CK12.
The output of the shift register 59 and F are used to form the clock CK13.

The content Lll of the latch 41 that changes in synchronization with the clock CKII and the content L12 of the latch 42 that changes in synchronization with the clock CK12 are shown in FIG. The content L11 of the latch 41 is 16-bit parallel data backed by the above-described embodiment. The content L12 of the latch 42 is obtained by sampling 11 of the contents of the latch 41 with the clock CK12.

The phase shifter 32 has the contents L of the latches 41 and 42.
32 bits of ll and L12 are input. Shift control signal φ that controls the bit shift amount of the phase shifter 32
is generated in synchronization with the clock CK13 from the clock generation circuit 35, as shown in FIG. 6E. The shift control signal φ is [0°10, 4. 14. 8. 2. 1
2. '6) is one sequence.

When the shift control signal φ is O, no shift operation is performed, and the top 10 bits of the input data of the phase shifter 32 are taken out as output, and the first word is taken out.

Next, when the shift control signal φ is 10, the phase shifter 32 generates 10 bits from the 11th bit of the input data as output. If the input data of the phase shifter 32 changes during the period in which the shift control signal φ is 10, the output data also changes accordingly. Due to the shift control signal φ shown in FIG. 6, the 10-bit output data from the phase shifter 32 becomes as shown in FIG. 6F.

The latch 43 samples and captures the output data of the phase shifter 32 using the clock CK13. Therefore, the content L13 of the latch 43 is as shown in FIG.
One word is 10 bits of data that changes in parallel in a regular order.

Even if the output data is not shown, it can be stored in a buffer memory such as FIF.
It is also possible to convert the data into data having a constant word clock by supplying the data to O.

(Effects of the Invention) According to the present invention, when data is transmitted via a transmission line in which n bits constitute one word and m bits (n≠m) constitute one word, the transmission line The transmission capacity of the phase shifter can be fully utilized and high-speed data transmission can be achieved.Furthermore, the present invention provides a sequence of the shift control signal φ that controls the shift amount of the phase shifter and the clock mask signal. It can be set by a CPU and a keyboard, and has the versatility of being compatible with various data bit numbers and transmission path bit numbers.This invention is useful when data reproduced from a recording medium is transferred to a computer. When applied to a computer, there is no need for preprocessing of unbacking data by a program on a computer, which has the advantage of reducing the burden on the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a block diagram of a control al11 circuit in an embodiment of this invention, and FIG. 3 is a time chart for explaining the operation of an embodiment of this invention. , FIG. 4 is a block diagram of another embodiment of this invention, FIG. 5 is a block diagram of a clock generation circuit in another embodiment of this invention, and FIG. 6 is an explanation of the operation of another embodiment of this invention. This is a time chart for Explanation of main symbols in the drawings t, al: input terminal, 2.32: phase shifter, 3.
33: Output terminal, 5: Control circuit, 6. '36: CPU,
22, 45, 52: RAM. Michibu Uga, Commissioner of the Patent Office1. Display of the case 1985 Patent Application No. 13151 2, Name of the invention Digital data processing circuit 3, Person making the amendment Relationship to the case Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Store Name ( 2
18) Sony Corporation Representative Director Norio Ohga 4, Agent 170 Address 1-48-10-6 Higashiikebukuro, Toshima-ku, Tokyo Subject of amendment 4 Brief description of drawings 7 Contents of amendment 1゜In the specification, Page 19, lines 1-'5, "Time chart"
and ``.'', ``, Figure 7 is a route map used to explain the conventional digital data processing circuit.'' is added.

Claims (1)

[Scope of Claims] At least two latches corresponding to the number of bits of the input data and connected in series, a shifting means to which outputs from the latches are supplied in parallel, and the number of bits of the input data. and a circuit that generates data for setting the shift amount of the shifting means based on the number of bits of the output data, and outputs output data having a number of bits different from the number of bits of the input data. Digital data processing circuit.