JPS6132291A - Memory device - Google Patents

Abstract

PURPOSE:To simplify reading and writing by supplying a column address strobe signal at a reverse phase after row address strobe signals are supplied in a page mode to N-number of memory blocks divided into two parts each. CONSTITUTION:Digital color video signals of one frame written on memory blocks 1 and 2 are read out through an address control similar to the writing. At the time of reading, data as shown in the figure J is outputted from the memory block 1, while data as shown in the figure K is outputted from the memory block 2. Output data of the memory blocks 1 and 2 are alternately selected by a selector 6, and accordingly the digital color video signal can be read out as shown in the figure L. Thus a clock system can be simplified, and a substrate can be scaled down, thereby facilitating the layout of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention is applicable to, for example, a 256-bit dynamic RA.
The present invention relates to a memory device suitable for configuring a frame memory using M.

[Conventional technology]

The frame memory has conventionally been composed of 64 64-bit dynamic RAMs. When the sampling period of the digital video signal is, for example, 70 nsec, it is not possible to write or read the digital video signal in real time due to access time constraints of the dynamic RAM. It had been.

By the way, due to advances in semiconductor technology, 256
Dynamic RAM is becoming relatively easy to obtain. However, the access time is still insufficient, and it is necessary to perform parallelization processing at the time of writing and serialization processing at the time of reading.

[Problem that the invention seeks to solve]

When a large number of dynamic RAMs are used in the past, and input digital video signals are written in parallel and read out in series, the scale of the hardware becomes large, timing control becomes troublesome, and it becomes difficult to check the circuits. There was a drawback.

An object of the present invention is to provide a memory device that does not require input data to be written in parallel and can realize a frame memory using a 256-bit dynamic RAM.

[Means for solving problems]

This invention consists of 2N dynamic RAMs, and after dividing the dynamic RAM into two memory blocks of N memory blocks and supplying a row address strobe signal port ℃ to each memory block in page mode,
Column address strobe signals CAS are supplied in opposite phases to each memory block.

[Effect]

Using the page mode in which the row address strobe signal RAS is fixed and the column address strobe signal CAS is changed, input data is written alternately to two memory blocks in real time without manually parallelizing the data. be able to.

Therefore, a frame memory can be realized using 2N dynamic RAMs of 256 bits.

〔Example〕

An embodiment in which the present invention is applied to a frame memory will be described below with reference to the drawings.

In FIG. 1, 1 and 2 indicate memory blocks, respectively. On the other hand, Memory Pro 1 has eight 256-focus dynamic RAMIA, IB.

IC, ID, IE, 1. Similarly, the other memory block 2 is composed of eight 256-bit dynamic RAMs 2A to 2H. Reference numeral 3 denotes an input terminal to which, for example, a still image color video signal for one frame is supplied. This input color video signal is supplied to an A/D converter 5 via a low pass filter 4.

The A/D converter 5 has a sampling frequency of 4 fsc (fsc is a color subcarrier frequency),
A digital color video signal of 8 bits per sample is generated, and this digital color video signal is supplied to memory blocks 1 and 2. The digital color video signals read from the memory blocks 1 and 2 are supplied to the selector 6, and the read outputs of the memory blocks 1 and 2 are alternately selected by the control signal from the terminal 7, and the D/A
The signal is supplied to a converter 8, converted into an analog signal, and taken out to an output terminal 10 via a low-pass filter 9.

11 indicates an address counter that generates a 9-bit column (colum+n) address, and 12 indicates an address counter that generates a 9-bit row (row) address. The outputs of these address counters 11 and 12 are supplied to an address selector 16.

The column address or row address from the address selector 16 is commonly supplied to the dynamic RAMIA-IH of the memory block 1 and the dynamic RAM2A-2H of the memory block 2.

The address counter 11 is supplied with a sampling clock SC synchronized with the input still image color video signal as a clock input, and a horizontal synchronization pulse H as a clear pulse. The address counter 12 is supplied with a horizontal synchronizing pulse (2) as a clock input and also with a vertical synchronizing pulse V as a clear pulse. In other words, dynamic RAMIA~IH, 2A~2H
The row addresses (0 to 511) are taken as line addresses, and the column addresses (0 to 511) are taken as sample addresses within the line.

``When an NTSC color video signal is sampled at a frequency of 4 fsc, a frame consists of 525 lines, and each line contains 910 samples. However, the valid data in one frame fits within 512 lines. .

The horizontal synchronizing pulse ■ is passed through the inverter 17 to become the row address strobe signal port °C, and the memory block 1
and 2 dynamic RAMs. The temperature between the row address strobe signals is used as a control signal for the address selector 16 via the delay circuit 18.

The least significant bit (LSB) of the column address output from the address counter 11 is used as the column address strobe signal α℃1 of the memory block 1 via the delay circuit 19 that compensates for data delay. A signal obtained by delaying the signal α°C1 by 70 nsec in the delay circuit 20 is the column address strobe signal α°C for the memory block 2.
2.

The least significant bit of the column address is the sampling period (14
0n5ec), the delay circuit 20 forms column address strobe signals of opposite phases for memory block 1 and memory block 2.

The address strobe signal is a control signal for reading address information on the address bus at appropriate timing. Furthermore, although not shown, a write enable signal for controlling writing and reading is supplied to each of the memory blocks 1 and 2.

FIGS. 2 and 3 are time charts of write and read cycles of the dynamic RAM used in one embodiment of the present invention.

As shown in FIG. 2A, the row address strobe signal n falls, the row address is read as shown in FIG. 2C, and then, as shown in FIG. 2B, the column address strobe signal α falls, and the column address is read as shown in FIG. 2C. Then, when the write enable signal type shown in the second diagram falls, the manual data Din is written as shown in FIG. 2E.

Also during reading, the row address strobe signal Fm and column address strobe signal α shown in FIGS. 3A and 3B are used.
By η, the address is centered as shown in FIG. 3C. Then, when the write enable signal type shown in Figure 3 rises, output data Dout is read out from the dynamic RAM as shown in Figure 3.

In the page mode, write and read cycle operations shown in the time charts of FIGS. 4 and 5 are performed.

As shown in Figure 4A, row address strobe signal port ℃
is brought low to set the row address, then
If the column address strobe signal α°C falls twice, for example, as shown in FIG. 4B while the row address strobe signal port ℃ remains at a low level, the address shown in FIG. 4C will be obtained. , only the column address changes.

By using the write enable signal type shown in the fourth diagram, input data can be written to two addresses that have a common row address and differ only in column addresses.

The page mode read cycle is also performed in the same way as the write cycle, as shown in FIG.

That is, by using the address strobe signals shown in FIGS. 5A and 5B, the address shown in FIG. 5C, where the row address is common and only the column address changes, is sent.
With the write enable signal type shown in Figure 5, output data D is output from the dynamic RAM as shown in Figure 5E.
out can be read.

This invention operates each of memory blocks 1 and 2 in page mode. FIG. 6 is a time chart of this embodiment.

FIG. 6A shows a horizontal synchronization pulse (3) synchronized with the digital color video signal from the A/D converter 5. FIG. This horizontal synchronizing pulse H is supplied to the address counter 12,
A row address that changes every horizontal period is formed, and is passed through the inverter 17 to generate a row address strobe signal ℃ as shown in FIG. and 2. Further, from the row address strobe signal word, the delay circuit 18 generates a control signal shown in FIG. This row address is then supplied to memory blocks 1 and 2. As shown in FIG. 6F, in the illustrated example, the row address is set to O.

The address counter 11 is cleared by the horizontal synchronization pulse H, and when this cleared state is released, the address counter 11 starts counting operation by the sampling clock SC, and the column address is incremented as shown in FIG. 6F. do. 1 is formed from the least significant bit of this column address by the column address strobe signal α shown in FIG. 6, and is supplied to the memory block 1. Delay circuit 20 forms column address strobe signal .alpha.2 for memory block 2 shown in FIG. 6E.

The write enable signal f1 shown in FIG. 6G is supplied to the memory block 1, the write enable signal f2 shown in FIG. 6H is supplied to the memory block 2, and the input data Din shown in FIG. One sample data is alternately written to memory block 2.

The first sample data of one horizontal period is stored in memory block 1.
When written to dynamic RAMIA~IH of memory block 2, the next sample data is written to dynamic RAMIA~IH of memory block 2.
Written to AM2A-2H. When this operation is repeated and the next horizontal synchronizing pulse ■ is supplied, the address counter 11 is cleared, the column address returns to its initial value, and the row address is incremented by +1. The column address of a dynamic RAM of 256 bits varies in the range (0 to 511), thus at most 10 bits in one horizontal period.
24 sample data can be written.

As described above, one frame of digital color video signals written in memory blocks 1 and 2 is read out using the same address control as when writing. During reading, the data shown in FIG. 6J is output from memory block 1, and the data shown in FIG. 6K is output from memory block 2.
Output from.

Then, the output data of memory blocks 1 and 2 are alternately selected by the selector 6, and the digital color video signal can be read out as shown in the sixth diagram.

Note that the dynamic RAM paste refresh may be performed during the blanking period. Further, the present invention can also be applied when a color video signal is separated into a luminance signal and two color difference signals for processing.

Furthermore, even when the number of bits in one sample is other than 8 bits,
It is sufficient to use the number of dynamic RAMs depending on the number of bits.

〔Effect of the invention〕

Unlike conventional memory devices, this invention parallelizes input data for each multiple sample when writing, does not require serialization of read data when reading, eliminates the need for a serial-to-parallel converter, and simplifies peripheral circuitry. It can be made into something. Therefore, the clock system becomes simple, the board size can be reduced, and the board layout becomes easy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of this invention, and FIGS. 2 and 3 are dynamic RA in one embodiment of this invention.
FIGS. 4 and 5 are time charts showing write and read cycles of the dynamic RAM in page mode in an embodiment of the present invention. FIG. It is a time chart used to explain the operation of the example. 1.2: Memory block, IA to IH, 2A to 2H: Dynamic RAM, 3: Input terminal, 5: A/D converter, IO: Output terminal, 11.12 Near address counter. (! El Duke of Rollo (c! e1 (, ; l mouth Duke = Duke of Rollo - Ro-ichi 1 2- -l:l:1g Ro - < = Ro Ro Country

Claims (1)

[Claims] A memory was configured using 2N dynamic RAMs, the dynamic RAM was divided into two memory blocks each having N memory blocks, and a row address strobe signal @RAS@ was supplied to each of the memory blocks in page mode. A memory device characterized in that the column address strobe signal @CAS@ is later supplied in opposite phase to each of the memory blocks.