JPS60243696A - Expansion data generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an enlarged data generation device for a memory device in which bit access is not possible.

(Structure of conventional example and its problems) CRT displays play an important role as a man-machine interface, but with the recent development of CAD and OA, they are increasingly used for graphic processing. When performing enlarged display in such a case, an efficient enlarged data generation device is required.

A conventional enlarged data generation device for a memory device incapable of bit access will be described below.

Figure 1 shows a block diagram of a conventional enlarged data generator, in which 1 is a rate multiplier that divides a timing signal (hereinafter referred to as CLK) by an enlargement rate, and 2 is a unit that holds original data of one word length. A first shift register that shifts 1 bit toward the MSB side according to the output signal of the rate multiplier, 3 is a 1-bit flag register that holds the carry data of the first shift register 2, and 4 is a holding register. This is a second shift register that shifts the one-word length data by one bit and stores the contents of the flag in the LSB every time CLK is input.

The operation of the conventional enlarged data generation apparatus for a memory device in which bits cannot be accessed as configured above will be described below. CLK by 1 with rate multiplier 1
The first shift register 2, which holds the original data of one word length, shifts one bit to the MSB side in synchronization with the signal obtained by dividing the /M expansion ratio. The second shift register 4 shifts the data held by the flag register 3 by 1 bit in synchronization with CLK, and converts the contents of the flag register 3 into the LSB.
, to create enlarged data in which the contents of the flag register 3 are stored in M bits each.

However, with this expansion method, if one word length is WL bits, it takes WLXCLK to create expanded data of one word length.
This method requires a long time and has the disadvantage of being slow.

(Object of the Invention) The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an enlarged data generation device that can quickly create enlarged data in a memory device that cannot access bits.

(Structure of the Invention) The present invention is an enlarged data generation device equipped with a shift register, a 1-bit flag register, a bit point register, and a gate control circuit, which rapidly creates enlarged data in a memory device that cannot access bits. It is something that can be done.

(Description of Embodiment) FIG. 2 is a block diagram showing the configuration of an enlarged data generation device in a memory device incapable of bit access according to an embodiment of the present invention. In Figure 2, 2 is 1
A shift register that holds the original data of the word length and shifts 1 bit to the MSB side each time a control signal is input, 3 is a 1-bit flag register that holds the carry data of shift register 2, and 5 is an expansion value that holds the expansion magnification rate. A register 6 is a bit point register that holds a bit pointer value indicating a bit position within one word; 7 is an adder that adds the contents of the enlarged value register 5 and the contents of the bit point register 6;
Reference numeral 8 designates a gate control circuit that selects bits of a register to be described later based on the contents of the bit point register 6, and reference numeral 9 designates an expanded data register that stores the contents of the flag register 3 in all bits selected by the gate control circuit 8.

The operation of the enlarged data generator of this embodiment configured as described above will be explained below with reference to FIGS. 3 and 4.

FIG. 3 shows the contents of the shift register 2 and the enlarged data register 9 when the enlargement factor is 4. FIG. 4 shows the relationship between the bit point register 6 and the enlarged data register 9. When the control signal is input, the shift register 2, which maintains the contents shown in FIG. is held and the bit point register 6 points to the 0th bit as an initial value, all gates of the gate control circuit 8 are opened (Fig. 4), and all bits of the enlarged data register 9 are set to the flag register. 3 contents S. is stored (Figure 3 (a))
. When the second control signal is input, shift register 2
is shifted by 1 bit to the MSB side, and 8 is stored in flag register 3.
1 is held, and at the same time the contents of the expansion value register 5 which holds the expansion magnification rate and the contents of the hit point register 6 are added, the bit point register 6 points to the 4th bit, and all the gates from the 4th bit onward of the gate control circuit 8 are is opened, and the contents of the flag register 3 are stored in the fourth and subsequent bits of the enlarged data register 9 (FIG. 3). When the third control signal is input, shift register 2 changes to MS.
Shifted by 1 bit to the B side, 82 is held in the flag register 3, and at the same time, the enlargement value register 5 holds the enlargement magnification rate.
and bit point register 6 points to the 8th bit,
All gates after the 8th bit of the gate control circuit 8 are opened, and the content S2 of the flag register 3 is stored in the 8th bit and after of the enlarged data register 9 (FIG. 3(1)).

When the fourth control signal is input, shift register 2 shifts one bit to the MSB side, and flag register 3 receives 83 bits.
is held, and at the same time, the enlarged value register 5 that holds the enlargement factor and the register 6 point to the 12th bit to bit point 1, and all gates after the 12th bit of the gate control circuit 8 are opened and the enlarged data register 9 is opened. The content S3 of the flag register 3 is stored from the 12th bit onwards (the 3rd bit
Figure (o)).

As described above, according to this embodiment, by providing the shift register, bit point register, flag register, and gate control circuit with dedicated hardware, in the case of expansion multiplier M, one word length (WL bit) can be expanded. Data creation takes only WL/M x CLK time, and high-speed creation is possible.

Note that in this embodiment, the case where the magnification factor is 4 is used, but it goes without saying that an arbitrary magnification factor (however, lower than WL) is also possible.

Further, in the above embodiment, the case of shifting to the MSB side was shown, but it goes without saying that the same effect can be obtained by shifting to the LSB side and selecting the gate from the LSB side.

(Effects of the Invention) The enlarged data generation device of the present invention is equipped with a shift register, a 1-bit flag register, a bit point register, and a gate control circuit, so that enlarged data can be created at high speed in a memory device that cannot access bits. can be carried out, and its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional enlarged data generator, FIG. 2 is a block diagram of an enlarged data generator according to an embodiment of the present invention, FIG. 3 is an operational diagram, and FIG. 4 is a bit diagram of an enlarged data generator. FIG. 3 is a diagram showing the relationship between a point register and an enlarged data register. 2. Shift register, 3.. Flag register, 5.. Expansion value register, 6.. Bit point register, 7.. Adder.
Gate control circuit, 9...Expansion data register. Figure 1 is the main line ν, and Figure 2 is 5. Figure 3 is IJ.
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Claims (1)

[Claims] The length of one word of the original data consisting of a plurality of words is held, and each time a control signal is input, M S B (Most 51gn1fi
cantBit ) side, and a 1-bit flag register that holds the carry (overflow) data of the shift register. a one-word enlarged data register provided for the purpose of accumulating enlarged data; a bit point register in which a pointer pointing to the bit position of the enlarged data register is updated by the number of enlargement factors each time the control signal is input; Using the contents of the bit point register as input, L after this bit pointer value
S B (least Significant Bi
t) a gate control circuit that generates a signal for selecting all the bits of the expanded data register on the side; and means for simultaneously transferring signals to a plurality of bits of the expanded data register selected by the path. Enlarged data generator.