JPH0120513B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to data processing in real-time processing by a processor such as a microprocessor.
The present invention relates to a RAM table writing method, and particularly relates to a data RAM table writing method in which writing can be executed at high speed based on a horizontal writing position flag when the data to be written is "1" or "0".

(b) Prior Art and Problems FIG. 1 is a diagram illustrating the configuration of equipment necessary for writing data RAM tables. In the figure, C is a data RAM table with 8-bit bytes as one word and storage locations from 0 to N, and A is data RAM table.
A horizontal write position flag (SNWF) consisting of, for example, 1 byte with the same bit length as one word of RAM table C, B is a vertical write position counter (N-ary counter) that indicates the storage position of data RAM table C, and D is a Register E is write data.

FIG. 2 is a diagram showing an example of a conventional data RAM table writing method.

The conventional data is shown below according to Figures 1 and 2.
Explain how to write to RAM table.

It is now assumed that the horizontal direction write position flag A (SNWF) and the write data E are as shown in a of FIG. That is, horizontal writing position flag A (SNWF)
The data is 11110111, and bit 3 is “0”.
is a flag indicating the write bit position.

It is assumed that the write data is the value shown in bit 7 of the write data E (indicated by diagonal lines).

First, it is tested whether the "0" bit of the horizontal write position flag A is at the bit 7 position (processing step 10 in Figure 4). Write position flag A
(SNWF) flag is moved to the left by 1, and at the same time the data shown in bit 7 of write data E is moved to the right by 1.
1 (processing steps 11 and 12), and returns to processing step 10 to test whether the flag has arrived at bit 7 of the horizontal write position flag A. If you repeat this operation four times, the horizontal write position flag A (SNWF) will be at the leftmost position, and the diagonally shaded part of write data E will be at the bit 3 position, as shown in Figure 2c. In processing step 10, it is detected that the flag has arrived at bit 7 of the horizontal writing position flag A, and the process branches to processing step 13.

Data RAM table C in processing step 13
One byte of data is read from the storage position n indicated by the vertical write position counter B to the register D, and in processing step 14, among the one byte data,
Erase only bit 3 as shown in d in Figure 2 and set it to “0”.
shall be.

Next, erase bits other than bit 3 of the write data E that has been shifted four times as shown in c in FIG. 2 to obtain data as shown in e in FIG. OR with the data as shown in d in the figure to generate data as in f in Fig. 2 (processing steps 15 and 16), and store this data in the vertical write position counter in the data RAM table C. Write to the location indicated by B (processing step 17).

In this way, the contents of the write data E were stored in the data RAM table C sequentially. However, this type of shift method has the disadvantage that the processing time is long, and the processing time varies greatly depending on the position of the flag.

(c) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a data RM table writing method that can be processed at high speed and within a certain amount of time.

(d) Structure of the Invention According to the present invention, the above object is achieved by controlling a processor to write a word on a data RAM table indicated by a vertical write position counter.
When writing bits specified as write data to the bits designated as write data by the flag set in the horizontal write position flag, which has bits corresponding to each bit of the word, the vertical write position counter The data indicated
Reads one word of data on the RAM table, and if the write data is “0”, data with all horizontal write position flags set to “0” and all other bits set to “1” and the read data, and if the write data is "1", all the horizontal write position flags are set to "1" and all other bits are set to "0". The data RAM is characterized in that it generates logical sum data of the read data and the read data, and writes the generated data to a storage position indicated by the vertical write position counter on the data RAM table. This is achieved by providing a table writing method.

(e) Embodiments of the Invention The main point of the present invention is to judge whether the data to be written is "1" or "0" and to write the data into the RAM table at high speed without affecting other bits. Take out 1 horizontal byte of data indicated by the write position counter, AND or OR with the horizontal write position flag to write only the bit indicated by the horizontal write position flag and the vertical write position counter,
The 1-byte data that has been written is returned to its original position.

FIG. 3 is a diagram showing an embodiment of the data RAM table writing method according to the present invention, and FIG. 5 is a flow chart of the process according to the present invention.

The details of the present invention will be explained below with reference to FIGS. 1, 3, and 5.

Now, let us consider the case where data "1" or "0" [data shown in bit 7 of write data E (indicated by diagonal lines)] which are continuously input is to be stored in the read data RAM table C.

At this time, it is assumed that the horizontal writing position flag A and the vertical writing position counter B are in the states shown in FIG. 1, respectively.

That is, it is assumed that the horizontal writing position flag A is 11110111 and the vertical writing position counter B is n.

First, 1-byte data of the n-th bit of data RAM table C is read into register D (processing step 20 in FIG. 5).

Next, in processing step 21, the write data is identified, and when the write data is "1" [when the data shown in bit 7 of the write data E (indicated by diagonal lines) is "1"], the horizontal write position flag is set. A
is inverted (processing step 22), and the inverted value is
That is, the logical sum (OR) is performed between 00001000 and the data 10101010 in register D (processing step 23), the result 10101010 is stored in register D, and the value of register D is stored in data RAM table C. The data is written to the storage position indicated by the vertical write position counter B (processing step 24).

When the write data is "0", the logical product (AND) is performed between the value of the horizontal write position flag A, that is, 11110111, and the data 10101010 of register D (processing step 25), and the result is 10100010. is stored in register D, and the value of register D is further written to the storage location indicated by vertical write position counter B in data RAM table C (processing step 24).

Through such operations, the data of the write data E is sequentially stored in the data RAM table C.

In the write method according to the present invention, for example, in an embodiment using a microprocessor with a 2 MHz clock, the write time is 16.5 .mu.S to 17 .mu.S, which is much faster than the 28 .mu.S to 70 .mu.S of the conventional method.
In the above description, the value of the flag indicating the write position is set to "0", but it is clear from the above description that the present invention can be similarly applied even if the value of the flag is "1". Further, although the description has been made assuming that the number of bits to be written at one time is one, it is clear from the above description that the present invention can be similarly applied to the case where the same write data is written to two or more bits at the same time.

(f) Effects of the Invention As described above in detail, the present invention has the great effect of significantly shortening the processing time, which has a great impact on the real-time processing of a microprocessor.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the configuration of equipment necessary for data RAM table writing. FIG. 2 is a diagram showing an example of a conventional data RAM table writing method. Figure 3 shows data RAM according to the present invention.
FIG. 3 is a diagram illustrating an example of a table writing method.
FIG. 4 is a flowchart of conventional processing, and FIG. 5 is a flowchart of processing of the present invention.

Claims (1)

[Scope of Claims] 1. Under the control of the processor, for one word on the data RAM table indicated by the vertical write position counter, a horizontal write position flag having bits corresponding to each bit of the word is set. The bits instructed to be written by the flags are
When writing the bit specified as write data, read one word of data on the data RAM table indicated by the vertical write position counter, and if the write data is "0", write the horizontal write data. Generates logical product data of the read data and data with all position flags set to "0" and all other bits set to "1", and if the write data is "1", the corresponding data is Set all horizontal writing position flags to “1”,
Generates logical sum data of the data with all other bits set to “0” and the read data, and stores the generated data in the storage location indicated by the vertical write position counter on the data RAM table. Data characterized by writing
RAM table writing method.