JPH10289202A - Microcomputer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for mutual timing designing between signal lines by using signal lines that share a command and an address that a CPU sets when writing or reading data to or out of a memory or peripheral circuit with a data signal line. SOLUTION: In a 1st cycle, the CPU sets a control command instructing writing or reading on a common bus signal line of 64-bit width. In a 2nd cycle, the CPU sets a 64-bit address on the common bus signal line of 64-bit width. In a 3rd cycle, the memory sets 64-bit data on the common bus signal line. Thus, a dedicated signal line is not prepared on a circuit board for a control signal and an address signal other than a data signal and the common signal line is used for all. The need for timing designing between the signal lines is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer circuit.

[0002]

2. Description of the Related Art When writing and reading data to and from a memory or a peripheral circuit in a microcomputer circuit, a CPU or another bus master first sets an address on an address-only signal line.

Next, a write command enable signal or a read command enable signal and a chip select enable signal are set. However, in some cases, these signal lines are generated by an external logic circuit. Also in this case, some signal lines such as an address enable, a data enable and a byte enable are set to generate these signal lines.

After all address signal lines and control signal lines have been set so far, it becomes possible to set write data or take in read data for the first time.

In the timing design of this series of operations, there are many elements which are timing parameters, such as an address signal line and a control signal line, or between control signal lines, as well as a set time for writing data and a time for taking in reading data. I do.

[0006]

The problem to be solved is that the same signal line is connected to a plurality of devices when increasing the speed and increasing the number of data bits on the circuit board of the microcomputer system. In addition, mutual timing design of control signal lines including address signals and impedance design of each control signal line on a circuit board become more complicated.

[0007]

According to the present invention, a microcomputer or a bus master in a microcomputer circuit on a board includes:
It is characterized by using a signal line shared with a data signal line without using a dedicated control signal line for a command and an address set when writing or reading data to or from a memory or a peripheral circuit.

[0008]

FIG. 3 is a circuit block diagram of the present embodiment. All the CPU, DMA controller, memory, and peripheral I / O IC are provided with circuit blocks for interface conversion with an external bus. This allows the common bus signal line of the present invention to be used as the external interface signal line even if the inside of the IC chip is constituted by the conventional interface signal line.

FIG. 2 is a timing chart of this embodiment. In this timing example, the case where the bus master is the CPU, the slave is the memory, the data bus width is 64 bits, and the command is read will be described.

In the first cycle, the CPU sets a control command such as write or read to a common bus signal line having a width of 64 bits. It is not necessary to use all the control commands for the 64-bit width. The control command may include a command relating to timing described later. The control command may include a chip select command for selecting an arbitrary memory IC from a plurality of memory ICs. The chip select command may not be provided from the CPU, but may have a logic for the memory IC to determine from the address.

In the second cycle, the CPU sets a 64-bit address on a 64-bit wide common bus signal line. If the address is 64 bits or more, the third cycle,
A fourth cycle is also required. Conversely, if the address is 64 bits or less, the setting can be made in one cycle together with the control command in the first cycle, and the second cycle becomes unnecessary.

In the third cycle, the memory sets 64-bit data to the common bus signal line. The CPU can acquire 64-bit data from the common bus signal line after the determined timing.

The individual cycle timing time, that is, the cycle in the previous cycle may be all fixed, or a timing setting command may be prepared as a command.

When a timing setting command is prepared as a command, a command for synchronizing the CPU and the memory may be provided to supply the system clock to the CPU and the memory.

[0015]

As described above, in the microcomputer circuit of the present invention, dedicated signal lines are not prepared on the circuit board for control signals and address signals other than data signals, and all signal lines are shared. This eliminates the need for timing design between signal lines. Since the number of dedicated signal lines is reduced and the timings at which the signal lines change are aligned, the problem of wiring mutual interference is reduced. Since the wiring impedances are almost the same, only a single kind of signal line needs to be designed for the wiring impedance.

Further, the number of dedicated signal lines can be reduced, so that the number of wiring patterns on the circuit board can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the timing of the related art.

FIG. 2 is an explanatory diagram showing a timing according to the embodiment of the present invention.

FIG. 3 is a block diagram of an embodiment of the present invention.

Claims (2)

[Claims] 1. In a circuit on a board that does not include the inside of an IC of a microcomputer circuit, commands, addresses, and data are all transmitted and received using the same system bus.
A circuit configuration that does not require a dedicated control signal line and address signal line when writing and reading data to and from a memory and peripheral circuits. 2. A command synchronized with the system clock, wherein a synchronization system clock is added to the circuit of claim 1.
A circuit configuration that does not require dedicated control signal lines and address signal lines when writing and reading data to and from memories and peripheral circuits by transmitting and receiving all addresses and data using the same system bus.