JPS62294283A - Personal computer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a video processing device for a personal computer (hereinafter referred to as a personal computer), and relates to a video processing device for a personal computer (hereinafter referred to as a personal computer). This relates to synchronization of the video processing section of the.

[Conventional technology]

Recently, there has been a function to import video signals from TVs, VCRs, and other video equipment as still images (hereinafter referred to as digitization), and a function to display a computer screen overlaid on images from a video etc. (superimpression). pose and when)
Many personal computers equipped with these functions are appearing on the market.

[Problem that the invention seeks to solve]

However, many of these conventional PCs only realize their functions when combined with a dedicated monitor, and in order to realize AV functions when connected to a home TV, they require the intermediary of an interface device that processes video. There were problems such as having to do it.

The real deal! 1q was created to solve the above-mentioned problems of the conventional method, and allows the basic functions of digitizing and superimposing to be realized even on a home TV without the need for an intermediary interface device such as in No. 111. The aim is to provide a highly expandable personal computer that can be used to

[Means for solving problems]

A personal computer according to the present invention includes a receiving section for receiving a video signal, a separating means for extracting a composite synchronizing signal from the video signal, a separating means for extracting a vertical synchronizing signal from the composite synchronizing signal, and a pseudo horizontal synchronizing signal. and phase synchronization means for controlling the frequency and phase of the horizontal synchronization signal to match those of the horizontal synchronization signal, and by initializing the phase synchronization means with the vertical synchronization signal, the video processing section This was done so that it could be synchronized with the

[Effect]

In the personal computer of the present invention, a synchronization signal separator extracts a composite synchronization signal from a video signal, further extracts a vertical synchronization signal from the extracted composite synchronization signal, and calculates the phase difference between these signals and a pseudo synchronization signal. A phase synchronization means detects and controls the frequencies and phases of the two to match, and the phase synchronization means is initialized by a vertical synchronization signal to compensate for deficiencies in the external video signal.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on FIGS. 1 to 5.

FIG. 1 is a circuit diagram of the main parts of an embodiment of a personal computer according to the present invention. 1 is a reference transmitter W (referred to as U-lower O8C), 2 is a frequency divider circuit that divides the OSCL output by N, and 3 is a phase In the synchronous circuit, 3a is a phase difference detection circuit that detects the frequency phase difference Δθ, 3bl is a low-pass filter circuit (hereinafter referred to as an LPF circuit), and 3C is a voltage control that changes the oscillation frequency based on the voltage value from the LPF circuit 3b. Transmitter (hereinafter referred to as VC)
O and when), 41! V CO3c (D output to 0
3c1 (7) Frequency divider circuit to make the same frequency as the output,
5 is a frequency divider circuit ■ which divides the frequency by N in the same way as the above frequency divider circuit ■2;
6 is a synchronization signal separator that extracts a synchronization signal from an external video signal (hereinafter referred to as V signal), and 6a is a composite synchronization signal separator that extracts a composite synchronization signal (hereinafter referred to as C5ync) from the V signal. The circuit 6b is a vertical synchronization signal molecule a circuit that extracts the vertical synchronization signal (hereinafter referred to as Vsync) in C5yne.

7a is a pulse timing generation circuit that performs pulse conversion based on the ■ signal when the period, phase, and pulse width of the V signal differs from predetermined values (standard values) due to a shifter, etc., and 7b similarly generates a pseudo synchronization signal, which will be described later. A pulse timing generation circuit performs pulse exchange based on the pseudo horizontal synchronization signal (hereinafter referred to as H5yne) from the generation circuit 8, and 8 generates an H! 9 is a gate signal generating circuit.

In addition, "ws" and "SW*" in the figure indicate analog switches, which are switched by 5EL (3rd order of No. 3).

FIGS. 2 to 4 are signal waveform diagrams of each part in FIG.

I The contents correspond to each other.

The operation of this embodiment will be described below with reference to FIGS. 2 to 4. First, the operation of the synchronous circuit will be explained based on the waveform diagram in FIG.

In Figure 1, the output signal from oscl is divided by the frequency dividing circuit
The signal Sl whose frequency is divided by N by 2 and the signal R whose frequency is divided by the frequency dividing circuit 4 and the frequency dividing circuit 5 of the Vco3c output.
The phase difference detection circuit 3n detects the frequency and phase difference with respect to 1 and converts it into an analog quantitative voltage value as shown in FIG.

In VCO3c, a predetermined reference voltage value (not shown) and the above V
Change the oscillation frequency by 2 depending on the difference in the voltage value of l. That is, the vco3C performs a follow-up operation so that S, = f'(,).

Next, the operation of extracting a synchronization signal from a video signal and generating a timing signal will be explained based on the waveform diagram of FIG.

From the V signal l from the video equipment etc., C5sync is extracted by the compound synchronization signal A3 branch circuit 6D portion of the synchronization signal separation unit 6, and VSyne is further extracted by the vertical synchronization signal separation circuit 6b portion. (FIG. 2 shows a diagram of the vertical synchronizing signal of the near part of the first field.) Further, the composite synchronizing signal is extracted by the composite synchronizing signal dividing circuit 6a:
C,' 5yne is used to ensure that the equivalent pulse of the vertical synchronizing signal near Q matches the period of the horizontal synchronizing signal, and to reliably catch disturbances in the period of the horizontal synchronizing signal and changes in pulse width due to jitter of the V signal, etc. , C5yne are converted into the period T of the signal S2 shown in FIG. 3 by the pulse timing generation circuit a.

Next, based on Fig. 4, the analog switch s is activated by the SEL signal.
When w,,sw change the contact point to the signal 83 side, that is,
Explain how external synchronization works.

As can be seen from the figure, the signal (2) does not come at a constant cycle due to jitter, etc., but has fluctuations in the cycle. However, based on the pseudo H5yne obtained by dividing the frequency of VCO3c, the pulse timing generation circuit b generates the signal R3, and as mentioned above, the phase synchronization circuit 3 becomes S, = R. Change the oscillation frequency of VCO3c.

■Since the signal cycle becomes faster or slower,
As shown in FIG. 4, the signal R1 is the signal S.

In order to follow the signal, it is necessary to detect the time difference between the signal S8 and the signal R, and if the frequency and phase match,
Δθ is set to the old GH level if the signal S is faster than the signal R3, and is set to the LOW level if the second signal St is slower than the signal R2, so that v■ becomes as shown in the figure. The voltage values above and below the predetermined reference voltage value of vCO3c are V
This will contribute to CO3c.

In addition, the VCO 3c changes the oscillation frequency so that S=R.

By the way, the ■ signal depends on the 81 device that generates it.
There is no distinction in the second field, there is no equivalent pulse, etc.), V5yn (H5ync near B is missing, etc.), and it requires complicated processing to adjust the external synchronization. The gate signal generation circuit shown in FIG. 1 can compensate for the above-mentioned parts and easily apply external synchronization.

This operation will be explained based on FIG. 5. The gate signal generating circuit 9 generates a pulse Gi when V and qyne fall, and further generates a pulse G2 when pulse G falls. The generation period @L of the pulse G2 is the period required to display the video, that is, the period for extracting the Hff31ne portion of only the portion visible on the TV screen. (,
A stable external synchronization circuit is constructed by separating only the signal defective portion of the Vsync portion.

Note that in this embodiment, the pulse timing generation circuit 7
If a, 7 and b are composed of monostable multi-oscillators, then
The time constant of this oscillator is 11:;9, so ``4
It is not a problem compared to the jitter etc. of No. A,
You can expect stable operation.

Further, in this embodiment, the minimum required configuration is shown, but there is no problem in configuring it using a video display processor IC, a display controller IC, or the like that can generate a C5yne or Hsync gold pseudo.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to achieve stable external synchronization and internal synchronization with a simple M circuit configuration, and it is possible to achieve stable external synchronization and internal synchronization with a simple M circuit configuration. The present invention can be implemented even on a -m home television without the need for a PC, and it is possible to provide a personal computer that is simple and highly expandable, unlike conventional PCs.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the main part of an embodiment of the great invention, Figure 2~
FIG. 5 is a signal waveform diagram for explaining the operation. In the figure, 3 is a phase synchronization circuit, 3a is a phase difference detection circuit, 3a
3b is the LPF circuit, 3b is the VCO 16 is the synchronization signal separation section, 6
a is a composite synchronizing signal separation circuit, and 6b is a vertical synchronizing signal component Ji.
ilDl path, 7n, 7b are pulse timing generation ri'
8 circuit, 8 indicates a pseudo synchronization signal generation circuit. Substitute Masuo Oiwa (2 others) Tan 1 Zuso 2 Kat I Yaku 3 Kuni

Claims (1)

[Claims] A receiving section that receives a video signal, a composite synchronization signal separation means that extracts a composite synchronization signal from the received video signal, a vertical synchronization signal separation means that extracts a vertical synchronization signal from the composite synchronization signal, and a reference oscillator output. Phase synchronization that controls the pseudo-horizontal synchronization signal by detecting the phase difference between the two so that the frequency and phase of the pseudo-horizontal synchronization signal obtained by frequency division match the frequency and phase of the horizontal synchronization signal from the synchronization signal separation means. means, and the video processing section can be synchronized with the external video signal by initializing the phase synchronization means with the vertical synchronization signal from the vertical synchronization signal separation means. personal computer.